Reduced Instruction Set Architecture (RISC)

• RISC is a design philosophy for computer architectures that emphasizes optimizing the execution of
a small and highly optimized set of instructions, each taking a single clock cycle to execute.

• In a RISC architecture, the instruction set is deliberately kept simple, with a reduced number of
instructions

• The instruction set is composed of a few basic steps for loading, evaluating, and storing operations
just like a load command will load data, a store command will store the data.

• The goal is to enhance the performance and efficiency of the processor by streamlining the execution
of instructions.

• Characteristics of RISC
o Instruction comes undersize of one word (simplifying the instruction fetch and decode stages
in the pipeline.)
o Instruction takes a single clock cycle to get executed, promoting faster instruction
throughput.
o More general-purpose registers (Arithmetic and logic operations primarily involve data
stored in registers rather than memory, reducing the need for memory access.)
o Simple Addressing Modes.
o Fewer Data types.
o A pipeline can be achieved. (Allowing multiple instructions to be in different stages of
execution simultaneously.)
o Adopt a load-store model, where data is explicitly loaded from memory into registers,
processed within the registers, and then stored back into memory.
o Hardwired Control Unit (RISC processors commonly implement a hardwired control unit,
using fixed logic circuits for instruction decoding and execution control.)

Advantages
• High Performance:
The simplicity of instructions and single-cycle execution contribute to high-speed processing.

• Efficient Pipelining:
Pipelining is well-suited to RISC architectures, allowing the overlap of instruction execution stages.

• Simplified Hardware Design:

The reduced instruction set leads to simpler hardware design, making RISC processors easier to
implement and optimize.

• Improved Register Usage:

RISC architectures emphasize register-based operations, reducing the need for memory access.

Disadvantages
• Increased Code Size:
RISC instructions are simpler, but more of them may be needed to perform complex operations,
 leading to larger code sizes. This can result in increased memory requirements and potentially impact
cache efficiency.

• Increased Memory Access:

RISC architectures typically use a load-store model, where most operations involve registers.
However, this can lead to increased memory access for loading and storing data, potentially
impacting performance in memory-bound applications.

• Higher cost:
Developing and manufacturing RISC processors can be more expensive than CISC processors.

• Compatibility Challenges:
Transitioning from CISC to RISC architectures or across different RISC architectures may pose
compatibility challenges. Existing software optimized for CISC architectures may not run as
efficiently on RISC architectures without modifications.

Complex Instruction Set Architecture (CISC)

• philosophy that emphasizes a large and rich set of complex instructions for a processor.

• In CISC architectures, instructions can perform multiple low-level operations or tasks in a single
instruction.

• A single instruction will do all loading, evaluating, and storing operations just like a multiplication
command will do stuff like loading data, evaluating, and storing it, hence it’s complex.

• Characteristics
o Rich Instruction Set:
CISC architectures have a diverse and extensive set of instructions, ranging from simple
operations to complex tasks.
o Variable-Length Instructions:
Instructions in a CISC architecture may have variable lengths, and some instructions can be
quite lengthy.
o Memory-Operands Access:
CISC instructions often allow direct access to operands in memory, reducing the need for
explicit load and store instructions.
o Specialized Instructions:
CISC architectures may include specialized instructions designed for specific tasks, such as
string manipulation or decimal arithmetic.

Advantages
• Reduced code size:
CISC processors use complex instructions that can perform multiple operations, reducing the amount
of code needed to perform a task.

• More memory efficient:

Because CISC instructions are more complex, they require fewer instructions to perform complex
tasks, which can result in more memory-efficient code.
 • Widely used:
CISC processors have been in use for a longer time than RISC processors, so they have a larger user
base and more available software.

• Reduced Program Development Time:

High-level instructions simplify programming, potentially reducing the number of instructions
needed for a given task.

Disadvantages
• Complexity:
The complex instruction set leads to intricate control units and instruction decoding logic, potentially
impacting processor complexity.

• Slower Clock Speed:

The execution of complex instructions may take multiple clock cycles, potentially reducing the
overall clock speed of the processor.

• Power Consumption:
The inclusion of complex instructions and additional circuitry may result in higher power
consumption.

RISC CISC

Focus on software Focus on hardware

Uses both hardwired and micropro-

Uses only Hardwired control unit
grammed control unit

Transistors are used for storing com-

Transistors are used for more registers
plex Instructions

Fixed sized instructions Variable sized instructions

Can perform only Register to Register Can perform REG to REG or REG to
Arithmetic operations MEM or MEM to MEM

Requires more number of registers Requires less number of registers

Code size is large Code size is small

An instruction executed in a single clock Instruction takes more than one clock
cycle cycle
 RISC CISC

Instructions are larger than the size of

An instruction fit in one word.
one word

Simple and limited addressing modes. Complex and more addressing modes.

RISC is Reduced Instruction Cycle. CISC is Complex Instruction Cycle.

The number of instructions are less as The number of instructions are more
compared to CISC. as compared to RISC.

It consumes the low power. It consumes more/high power.

RISC is highly pipelined. CISC is less pipelined.

RISC required more RAM. CISC required less RAM.

Here, Addressing modes are less. Here, Addressing modes are more.