Unit_2
Unit_2
From Unit 2: Computer Organization and Architecture, I’ll select the most important
and high-probability topics for your exam:
Answer: A
Explanation: 45 in decimal = 32 + 8 + 4 + 1 = 101101 in binary.
Answer: B
Explanation: Group binary digits in 3’s from right: 110 101 = 6 5 in octal.
Answer: A
Explanation: Group binary digits in 4’s: 1111 = F, 0010 = 2 → F2.
Answer: A
Explanation: 1’s complement is obtained by flipping all bits.
Answer: B
Explanation: 2’s complement = 1’s complement + 1 = 01010 + 1 = 01011.
Answer: A
Explanation: 1011 + 1101 = 11000 (with carry).
Answer: A
Explanation: Subtraction is performed by adding 2’s complement of subtrahend to minuend.
Answer: D
Explanation: Binary 7 = 0111, 1’s complement = 1000, add 1 → 1001.
Answer: A
Explanation: Convert subtraction to addition: 1101 + 2’s complement of 1001 (0111) = 1101 +
0111 = 10100 (ignore carry) = 0100.
Answer: B
Explanation: 1A = (1 * 16) + (10) = 26 decimal.
11. Which of the following is the binary representation of octal number 37?
A) 11111
B) 11101
C) 11011
D) 10111
Answer: A
Explanation: Octal 3 = 011, 7 = 111 → 011111 = 11111.
Answer: B
Explanation: 101 (5 decimal) × 11 (3 decimal) = 15 decimal = 11111 binary.
Answer: C
Explanation: 1100 (12 decimal) ÷ 10 (2 decimal) = 6 decimal = 110 binary.
Answer: D
Explanation: Hexadecimal is base-16 number system.
Answer: A
Explanation: (132)+(016)+(08)+(14)+(02)+(11)= 32+4+1=37.
16. What is the output of adding 1’s complement of 1101 and binary 1010?
A) 0111
B) 1001
C) 0101
D) 1111
Answer: A
Explanation: 1’s complement of 1101 = 0010; 0010 + 1010 = 1100 (carry ignored) = 0111.
Answer: B
Explanation: 2’s complement simplifies subtraction by converting it to addition.
18. How many bits are required to represent decimal number 255 in binary?
A) 6
B) 7
C) 8
D) 9
Answer: C
Explanation: 255 = 11111111 in binary → 8 bits.
Answer: B
Explanation: Complements (1’s and 2’s) simplify subtraction operations.
Answer: D
Explanation: Subtraction in binary can be done via borrowing or complement methods; 2’s
complement is most common.
1. Which error detection method adds an extra bit to data to make the number of 1s either
even or odd?
A) Checksum
B) Parity Bit
C) Hamming Code
D) CRC
Answer: B
Explanation: Parity bit adds a single bit to make total 1s count even (even parity) or odd (odd
parity).
2. In even parity, what should be the parity bit if the data bits are 1011?
A) 0
B) 1
C) 2
D) None
Answer: A
Explanation: Number of 1s = 3 (odd), parity bit must be 1 to make total 1s even.
3. Which error detection method divides data into segments and adds all segments to detect
errors?
A) Parity Bit
B) Checksum
C) Hamming Code
D) Cyclic Redundancy Check (CRC)
Answer: B
Explanation: Checksum divides data into equal segments and sums them to detect errors.
Answer: C
Explanation: Hamming code can detect and correct single-bit errors.
Answer: C
Explanation: Hamming code places parity bits at powers of two positions for error correction.
6. Which method is most suitable for detecting burst errors?
A) Parity Bit
B) Checksum
C) Hamming Code
D) Cyclic Redundancy Check (CRC)
Answer: D
Explanation: CRC is highly effective for burst error detection.
7. In Hamming code, how many parity bits are needed for 4 data bits?
A) 2
B) 3
C) 4
D) 5
Answer: B
Explanation: Number of parity bits p satisfies 2^p ≥ m + p + 1, for m=4 → p=3.
Answer: B
Explanation: Even parity means total 1s including parity bit is even.
Answer: D
Explanation: ASCII is a character encoding scheme, not an error detection method.
10. Checksum method is commonly used in:
A) Computer memory
B) Network communication
C) Database indexing
D) CPU arithmetic
Answer: B
Explanation: Checksum is widely used in network protocols for error detection.
Answer: A
Explanation: Parity bit fails to detect errors if an even number of bits are wrong.
Answer: A
Explanation: Hamming code can detect two-bit errors but correct only one-bit errors.
Answer: B
Explanation: Redundant bits help detect and correct errors.
14. Which of the following codes is a linear block code?
A) Parity bit code
B) Checksum
C) Hamming code
D) Gray code
Answer: C
Explanation: Hamming code is a linear block code used for error correction.
15. What happens when a single-bit error occurs in data protected by parity bit?
A) Detected by parity check
B) Undetected
C) Corrected automatically
D) Causes data loss
Answer: A
Explanation: Single-bit error changes parity, so it’s detected.
16. In checksum, the receiver adds all received segments including checksum to:
A) Check for sum overflow
B) Verify if the sum equals zero
C) Increase data size
D) Encrypt data
Answer: B
Explanation: Sum should be zero (or a fixed value) for no error.
Answer: C
Explanation: Hamming code efficiently corrects single-bit errors.
18. What type of code is Gray code?
A) Error detection code
B) Error correction code
C) Binary numeral system
D) Non-weighted code to prevent errors in digital systems
Answer: D
Explanation: Gray code changes only one bit between consecutive numbers, reducing errors.
Answer: C
Explanation: CRC uses polynomial division for error checking.
20. Which code can both detect and correct single-bit errors?
A) Parity bit
B) Checksum
C) Hamming code
D) ASCII
Answer: C
Explanation: Hamming code can detect and correct single-bit errors.
Answer: A
Explanation: ASCII (American Standard Code for Information Interchange) encodes characters
like letters, digits, and symbols.
2. How many bits are used in standard ASCII code?
A) 6
B) 7
C) 8
D) 16
Answer: B
Explanation: Standard ASCII uses 7 bits to represent 128 characters.
Answer: A
Explanation: EBCDIC (Extended Binary Coded Decimal Interchange Code) is an 8-bit character
encoding used mainly by IBM.
Answer: A
Explanation: BCD represents each decimal digit by its 4-bit binary equivalent.
Answer: A
Explanation: 9 in decimal is 1001 in 4-bit binary (BCD).
6. What is the main advantage of Gray code over binary code?
A) Faster computation
B) Only one bit changes between consecutive numbers
C) Smaller size
D) Used in error correction
Answer: B
Explanation: Gray code changes only one bit at a time, reducing errors in digital systems like
rotary encoders.
Answer: C
Explanation: Gray code is a non-weighted code where bit positions don’t have assigned
weights.
Answer: A
Explanation: Gray code is formed by XORing the binary number with its right-shifted version.
Answer: B
Explanation: BCD is weighted because each bit has positional value.
Answer: B
Explanation: EBCDIC is used mostly in IBM mainframe and midrange computer systems.
12. How many decimal digits can be represented by one byte in BCD?
A) 1
B) 2
C) 3
D) 4
Answer: B
Explanation: Each decimal digit uses 4 bits; 1 byte (8 bits) can represent 2 digits.
Answer: B
Explanation: XOR 1101 with 0110 (shift right by 1) = 1011.
15. Which code is best for minimizing errors in analog to digital conversion?
A) ASCII
B) Gray code
C) BCD
D) Parity bit
Answer: B
Explanation: Gray code minimizes errors by only changing one bit at a time.
16. ASCII uses how many bits to represent the character 'A'?
A) 5
B) 6
C) 7
D) 8
Answer: C
Explanation: 'A' in ASCII is 1000001 (7 bits).
Answer: A
Explanation: BCD directly encodes decimal digits in 4 bits.
Answer: A
Explanation: Gray code sequence: 011 → 010.
20. Which code would you use in digital systems to reduce switching errors?
A) ASCII
B) BCD
C) Gray code
D) EBCDIC
Answer: C
Explanation: Gray code reduces errors in digital encoders by limiting bit changes.
Answer: C
Explanation: A half adder adds two single-bit numbers and gives Sum and Carry as output.
Answer: B
Explanation: A full adder is made using two half adders and an OR gate.
Answer: A
Explanation: Sum = A ⊕ B = 1 ⊕ 1 = 0
Answer: B
Explanation: A decoder with 3 inputs has 2³ = 8 outputs.
Answer: C
Explanation: A multiplexer selects one of many inputs and forwards it to a single output line.
Answer: B
Explanation: For n inputs, number of select lines = log₂(n) = log₂(8) = 3.
Answer: B
Explanation: The decoder activates one of the outputs based on binary input combination.
Answer: B
Explanation: Parity generators are used to detect errors in digital data transmission.
Answer: A
Explanation: Number of 1s = 3 (odd), parity bit = 1 to make it even; So parity bit = 1.
Answer: B
Explanation: A decoder converts binary inputs to decimal output.
Answer: C
Explanation: It adds two 4-bit binary numbers.
Answer: B
Explanation: XOR gates are used to perform subtraction logic in digital circuits.
Answer: A
Explanation: An encoder takes 2ⁿ inputs and produces an n-bit binary output.
Answer: C
Explanation: Flip-flops are sequential circuits because they have memory.
15. What is the output of a 1-to-2 demultiplexer with input = 1 and select = 0?
A) Output 0 = 1, Output 1 = 0
B) Output 0 = 0, Output 1 = 1
C) Both outputs = 0
D) Undefined
Answer: A
Explanation: Select line = 0, so input goes to output 0.
16. In an odd parity system, which is the parity bit for 1100?
A) 1
B) 0
C) 2
D) Can't determine
Answer: A
Explanation: Number of 1s = 2 (even), so parity bit = 1 to make it odd.
Answer: B
Explanation: log₂(16) = 4 selection lines.
Answer: C
Explanation: XOR gate checks parity by detecting even/odd number of 1s.
Answer: C
Explanation: Decoders are widely used for selecting memory locations.
20. Which device can be used to implement any combinational logic function?
A) Decoder
B) Encoder
C) Multiplexer
D) Adder
Answer: C
Explanation: Multiplexers can implement any logic function when configured with the correct
input combinations.
Answer: C
Explanation: Flip-Flops are fundamental memory elements used in sequential circuits.
Answer: D
Explanation: The condition S = 1 and R = 1 is invalid for an SR Flip-Flop.
Answer: C
Explanation: D Flip-Flop transfers input D to output Q on the clock edge; T Flip-Flop toggles its
output.
Answer: B
Explanation: Feedback is used in JK Flip-Flops to resolve the undefined state.
5. What will be the output of a D Flip-Flop if D=1 and a rising edge clock is applied?
A) 0
B) 1
C) Toggle
D) No change
Answer: B
Explanation: D Flip-Flop transfers the D input to Q on the rising edge of the clock.
Answer: C
Explanation: When T = 1, the flip-flop toggles its output on each clock pulse.
Answer: C
Explanation: Each flip-flop stores 1 bit, so 4 are needed for a 4-bit register.
Answer: B
Explanation: Registers are used to store and move data within the system.
9. Which type of counter counts both up and down?
A) Ring counter
B) Ripple counter
C) Up-down counter
D) Johnson counter
Answer: C
Explanation: Up-down counters can increment or decrement the count based on control input.
10. In a 4-bit binary counter, what is the maximum count it can reach?
A) 8
B) 15
C) 16
D) 4
Answer: B
Explanation: A 4-bit counter can count from 0 to 15 (2⁴ – 1).
Answer: C
Explanation: A counter with n flip-flops has a modulus of 2ⁿ. So 2³ = 8.
Answer: C
Explanation: A Johnson counter is also known as a twisted ring counter.
13. What is the output of a T flip-flop if T = 0 and clock is applied?
A) Toggles
B) Resets
C) No change
D) Undefined
Answer: C
Explanation: When T = 0, the T Flip-Flop holds its previous state.
14. What is the initial state of a 3-bit shift register loaded with 101 and shifted right once?
A) 101
B) 110
C) 010
D) 010 with 0 shifted in
Answer: D
Explanation: Right shift pushes bits right, with 0 filling the MSB.
Answer: D
Explanation: T Flip-Flops toggle their output and are ideal for counting.
Answer: B
Explanation: A state table shows transitions from current to next states based on inputs.
17. What is the next state of a JK Flip-Flop when J = K = 1 and current state is 0?
A) 0
B) 1
C) Toggle to 1
D) Undefined
Answer: C
Explanation: JK with J = K = 1 toggles the output, so it becomes 1.
Answer: A
Explanation: In asynchronous (ripple) counters, flip-flops are triggered by the output of the
previous flip-flop.
Answer: A
Explanation: D Flip-Flops are commonly used in shift registers for bit storage and shifting.
Answer: C
Explanation: The clock signal synchronizes changes in state in sequential circuits.
Topic 4: Memory Types and Microprocessor Basics
A. ROM
B. EEPROM
C. DRAM
D. PROM
Answer: C. DRAM
Explanation: DRAM (Dynamic RAM) is volatile and loses data when power is turned off. ROM,
PROM, and EEPROM are non-volatile.
A. SRAM
B. PROM
C. EEPROM
D. DRAM
Answer: C. EEPROM
Explanation: BIOS is stored in EEPROM (Electrically Erasable Programmable Read-Only Memory)
as it needs to retain data even when power is off and be updated occasionally.
A. Hard disk
B. DRAM
C. SRAM
D. ROM
Answer: C. SRAM
Explanation: SRAM (Static RAM) is faster and more expensive than DRAM and is used for cache
memory.
A. PROM
B. EPROM
C. DRAM
D. EEPROM
Answer: C. DRAM
Explanation: DRAM is a type of RAM, not ROM. The others are all types of ROM.
5. In microprocessor systems, which bus is responsible for transferring data between CPU and
memory?
A. Address bus
B. Data bus
C. Control bus
D. Status bus
A. 8085
B. 8086
C. Z80
D. Intel 4004
Answer: B. 8086
Explanation: Intel 8086 was the first 16-bit microprocessor widely used in PCs.
7. How many lines are there in an address bus to access 64KB memory?
A. 8
B. 16
C. 32
D. 64
Answer: B. 16
Explanation: 2^16 = 65,536 = 64KB; hence 16 address lines are required.
Answer: B. EPROM
Explanation: EPROM can be erased using UV light and reprogrammed.
A. A small processor
B. CPU with memory and I/O ports
C. Advanced CPU
D. CPU with keyboard
A. Send addresses
B. Carry data
C. Manage signals like read/write
D. Store memory
A. SRAM
B. DRAM
C. ROM
D. PROM
Answer: B. DRAM
Explanation: DRAM stores each bit in a capacitor that leaks charge and thus requires refreshing.
12. Which type of ROM can be reprogrammed without removing it from the circuit?
A. PROM
B. EPROM
C. EEPROM
D. ROM
Answer: C. EEPROM
Explanation: EEPROM can be erased and reprogrammed electrically while in-circuit.
13. Which of the following has the highest data transfer rate?
A. Hard Disk
B. RAM
C. Cache
D. SSD
Answer: C. Cache
Explanation: Cache memory is closest to the CPU and has the highest speed.
A. BIOS
B. Secondary Storage
C. Cache Memory
D. Main Memory
A. SRAM
B. DRAM
C. ROM
D. HDD
Answer: A. SRAM
Explanation: Due to its speed and architecture, SRAM is the most expensive.
A. RAM
B. EEPROM
C. PROM
D. DRAM
Answer: C. PROM
Explanation: PROM can be programmed once after manufacturing and retains data
permanently.
A. ALU
B. Control Unit
C. CPU
D. Memory
Answer: C. CPU
Explanation: The CPU (Central Processing Unit) is the main component that executes
instructions.
A. Intel 4004
B. Intel 8086
C. Zilog Z80
D. Motorola 68000
A. Cheaper
B. Faster
C. Can be erased electrically
D. Uses less power
Key Takeaways:
SRAM is fast and used for cache; DRAM is slow but cheaper, used for main memory.
Microprocessor evolution started with Intel 4004; 8086 was the first PC microprocessor.
Control, data, and address buses each serve unique roles in communication.
1. Which logic gate has an output that is true only when all inputs are true?
A. OR
B. AND
C. NAND
D. NOR
Answer: B. AND
Explanation: AND gate outputs 1 only if all inputs are 1.
A. AND and OR
B. XOR and XNOR
C. NAND and NOR
D. AND and NOR
Answer: C. NAND and NOR
Explanation: NAND and NOR can be used to construct any logic gate.
A. (A + B)’ = A’.B’
B. (A.B)’ = A’ + B’
C. (A + B)’ = A + B
D. A + B = A.B
Answer: A. (A + B)’ = A’.B’
Explanation: This is the first of DeMorgan’s laws.
5. The SOP form of the Boolean expression A'B + AB' is an example of:
A. Half adder
B. XOR gate
C. NOR gate
D. NAND gate
Answer: B. XOR gate
Explanation: A'B + AB' is the standard form of A XOR B.
A. OR
B. AND
C. NOR
D. XOR
Answer: A. OR
Explanation: OR gate outputs 0 only when all inputs are 0.
A. Build computers
B. Perform arithmetic
C. Minimize Boolean expressions
D. Convert binary to decimal
Answer: C. Minimize Boolean expressions
A. 8
B. 16
C. 32
D. 64
Answer: B. 16
11. In a 2-variable K-map, how many adjacent cells does each cell have?
A. 1
B. 2
C. 3
D. 4
Answer: D. 4
A. 1 cell
B. 2 adjacent cells
C. 4 adjacent cells
D. 8 adjacent cells
Answer: C. 4 adjacent cells
A. Standard OR Product
B. Sum of Products
C. Sum or Product
D. Simple Output Processor
Answer: B. Sum of Products
A. Product of Sums
B. Power of Sums
C. Product of Signals
D. Position of Signals
Answer: A. Product of Sums
15. What is the output of an XOR gate when both inputs are 1?
A. 1
B. 0
C. Depends on input
D. Undefined
Answer: B. 0
A. Exclusive OR
B. Equivalence gate
C. Inverter
D. Half adder
Answer: B. Equivalence gate
Explanation: XNOR is 1 when inputs are equal.
A. XOR, XNOR
B. NAND, NOR
C. AND, OR
D. NOT, AND
Answer: B. NAND, NOR
A. Pair
B. Quad
C. Octet
D. Cell
Answer: C. Octet
A. A
B. 1
C. 0
D. A’
Answer: A. A
Explanation: A + A = A is an Idempotent Law in Boolean algebra.
A. 1
B. 0
C. A
D. A’
Answer: B. 0
A. 1
B. 0
C. A
D. A’
Answer: A. 1
A. AB
B. A
C. B
D. A + B
Answer: B. A
Explanation: Absorption Law.
A. A + B
B. B
C. A’
D. A
Answer: A. A + B
A. AND
B. OR
C. NAND
D. NOT
Answer: C. NAND
26. The total number of possible input combinations for 3 variables is:
A. 4
B. 6
C. 8
D. 16
Answer: C. 8
A. SOP
B. POS
C. Boolean
D. Minterm
Answer: C. Boolean
28. The term 'don’t care' in K-map is used to:
A. Increase complexity
B. Ignore valid outputs
C. Minimize expressions
D. Fill empty cells
Answer: C. Minimize expressions
A. 10
B. 12
C. 15
D. 8
Answer: A. 10
A. Associative
B. Absorption
C. Distributive
D. Demorgan
Answer: B. Absorption
Key Takeaways:
Master basic and universal gates (AND, OR, NOT, NAND, NOR, XOR, XNOR).
Practice Boolean simplification using laws like identity, null, complement, absorption.:
a) 0
b) 1
c) Depends on number of inputs
d) Cannot be determined
Answer: b) 1
Explanation: AND gate gives 1 only when all inputs are 1.
a) A·B
b) A + B
c) A ⊕ B
d) A'B
Answer: b) A + B
Explanation: The '+' symbol denotes logical OR.
6. Which gate has the truth table where output is 1 only when inputs are different?
a) AND
b) OR
c) XOR
d) NAND
Answer: c) XOR
Explanation: XOR outputs 1 only when inputs are different.
a) XOR
b) AND
c) OR
d) NOT
Answer: a) XOR
Explanation: XOR is commonly used in parity checkers.
a) (A + B)’
b) A’ + B’
c) (A·B)’
d) A’·B’
Answer: a) (A + B)’
Explanation: NOR is the negation of OR.
a) AND
b) OR
c) NAND and NOR
d) XOR
Answer: c) NAND and NOR
Explanation: DeMorgan’s laws relate NAND/NOR with basic gates.
a) 8
b) 12
c) 16
d) 32
Answer: c) 16
Explanation: 2⁴ = 16 cells.
a) AB
b) A
c) B
d) A + B
Answer: b) A
Explanation: A + AB = A(1 + B) = A
13. A logic circuit that outputs 0 when inputs are the same is:
a) NOR
b) XOR
c) AND
d) NOT
Answer: b) XOR
Explanation: XOR gives 0 for same inputs.
a) Product of Sums
b) Sum of Products
c) Sum of Complements
d) Product of Complements
Answer: b) Sum of Products
Explanation: SOP = OR (sum) of AND (product) terms.
a) AB
b) A
c) A + B
d) AB'
Answer: b) A
Explanation: (A + B)(A + B') = A
a) A’ + B’
b) A + B
c) A’·B’
d) (A + B)’
Answer: a) A’ + B’
Explanation: (A·B)’ = A’ + B’
a) Any size
b) Power of 2
c) Even numbers only
d) Prime numbers
Answer: b) Power of 2
Explanation: K-map groups: 1, 2, 4, 8, etc.
a) A·B
b) A + B
c) (A + B)’
d) A’ + B’
Answer: c) (A + B)’
Explanation: NOR is NOT-OR.
21. The logic gate with only one input and one output is:
a) AND
b) OR
c) NOT
d) NOR
Answer: c) NOT
Explanation: NOT inverts the input.
22. Which gate produces an output only when both inputs are not equal?
a) NAND
b) XOR
c) NOR
d) AND
Answer: b) XOR
Explanation: XOR gives 1 when inputs differ.
a) A
b) AB
c) B
d) A + B
Answer: a) A
Explanation: A·(A + B) = A
a) A + BC
b) AB + AC
c) A + B + C
d) A + BC
Answer: a) A + BC
Explanation: Apply distributive law and simplify.
a) 4
b) 6
c) 8
d) 10
Answer: c) 8
Explanation: 2³ = 8 combinations.
a) 1
b) 2
c) 4
d) 8
Answer: b) 2
Explanation: Pair = 2 adjacent 1s.
A | B | Output
0|0|1
0|1|0
1|0|0
1 | 1 | 0**
a) NOR
b) NAND
c) AND
d) NOR
Answer: a) NOR
Explanation: Only when both inputs are 0, output is 1.
a) AND and OR
b) AND and XOR
c) XOR and NOT
d) OR and XOR
Answer: b) AND and XOR
Explanation: XOR is used for SUM, AND is used for CARRY.
3. What is the carry output of a half adder when inputs are A=1 and B=1?
a) 0
b) 1
c) 2
d) Undefined
Answer: b) 1
Explanation: Carry = A AND B = 1
a) 1
b) 2
c) 3
d) 4
Answer: c) 3
Explanation: Full adder adds A, B, and Carry-in (Cin).
5. What is the minimum number of full adders required to add two 4-bit binary numbers?
a) 1
b) 2
c) 3
d) 4
Answer: d) 4
Explanation: One full adder for each bit.
a) A ⊕ B
b) A ⊕ B ⊕ Cin
c) (A·B) + (Cin)
d) A + B + Cin
Answer: b) A ⊕ B ⊕ Cin
Explanation: This gives the 1-bit sum.
7. What is the carry-out of a full adder with inputs A=1, B=1, Cin=1?
a) 0
b) 1
c) 2
d) 3
Answer: b) 1
Explanation: Carry = AB + BCin + ACin = 1
8. What is the sum output of full adder when A=1, B=0, Cin=1?
a) 0
b) 1
c) 2
d) 3
Answer: a) 0
Explanation: A ⊕ B ⊕ Cin = 1 ⊕ 0 ⊕ 1 = 0
9. What is the main difference between half adder and full adder?
a) Speed
b) Number of outputs
c) Number of inputs
d) Memory
Answer: c) Number of inputs
Explanation: Half adder has 2 inputs; full adder has 3 inputs.
a) Decoder
b) Encoder
c) Half and Full adders
d) Counter
Answer: c) Half and Full adders
Explanation: Binary adder circuits are constructed using these.
a) 4 half adders
b) 4 full adders
c) 4 multiplexers
d) 2 half + 2 full adders
Answer: b) 4 full adders
Explanation: Each full adder handles one bit and the carry from previous stage.
a) It uses multiplexers
b) Carry propagation takes time
c) It uses large memory
d) All outputs are generated at once
Answer: b) Carry propagation takes time
Explanation: Carries ripple through all stages.
a) Add A and B
b) Subtract A from B
c) Add A and 2’s complement of B
d) Subtract B from A directly
Answer: c) Add A and 2’s complement of B
Explanation: Subtraction is performed by adding the complement.
a) 0010
b) 0101
c) 1110
d) 0011
Answer: d) 0011
Explanation: Invert and add 1: 0010 + 1 = 0011
a) 0111
b) 1000
c) 0000
d) 1111
Answer: b) 1000
Explanation: 2's complement of a number is same when MSB is set and rest are 0.
a) Only addition
b) Only subtraction
c) Addition and Subtraction
d) Multiplication
Answer: c) Addition and Subtraction
Explanation: It uses XOR gates to flip bits for subtraction.
a) Logical AND
b) Bitwise XOR
c) Binary Addition
d) Shift
Answer: c) Binary Addition
Explanation: It adds two binary numbers.
a) 0
b) 1
c) 2
d) Undefined
Answer: a) 0
Explanation: AND(0,1) = 0
19. For A=1, B=0, Cin=1, what is sum and carry in full adder?
a) Sum = 0, Carry = 1
b) Sum = 1, Carry = 0
c) Sum = 1, Carry = 1
d) Sum = 0, Carry = 0
Answer: a) Sum = 0, Carry = 1
Explanation: A⊕B⊕Cin = 0, Carry = AB + BCin + ACin = 1
20. What is the advantage of using 2’s complement over 1’s complement?
a) More memory
b) Easier logic implementation
c) Slower speed
d) Less accurate
Answer: b) Easier logic implementation
Explanation: 2's complement avoids multiple representations of zero.
a) Carry = 0
b) Result exceeds fixed bit size
c) Subtraction occurs
d) All bits are 1
Answer: b) Result exceeds fixed bit size
Explanation: It cannot be represented in the fixed number of bits.
a) Generating carry
b) Generating borrow
c) Inverting bits of B
d) Performing AND
Answer: c) Inverting bits of B
Explanation: XOR with control bit flips B to perform subtraction.
a) Logical shifting
b) Arithmetic operations
c) Data storage
d) Memory addressing
Answer: b) Arithmetic operations
Explanation: It handles add, subtract, increment, etc.
a) OR
b) AND
c) XOR
d) NOT
Answer: b) AND
Explanation: Carry = A·B
a) 1011
b) 1110
c) 1010
d) 1011
Answer: d) 1011
Explanation: 5 = 0101; Invert = 1010, Add 1 = 1011
a) A=0, B=0
b) A=1, B=1
c) A=1, B=0
d) A=1, B=1
Answer: c) A=1, B=0
Explanation: XOR(1,0) = 1
28. Which part of the ALU gives the output for logic operations?
a) Arithmetic section
b) Logic section
c) Memory
d) Control unit
Answer: b) Logic section
Explanation: AND, OR, NOT, etc., are handled here.
a) 1001
b) 1010
c) 1011
d) 0111
Answer: a) 1010
Explanation: Invert 0110 = 1001; +1 = 1010
a) Carry bit
b) Control signal
c) MSB
d) Clock
Answer: b) Control signal
Explanation: It selects between add or subtract modes.