12 Physical Design Experiments for B.

Tech Students: Cadence Genus and Innovus

Experiment 1: RTL Synthesis with Cadence Genus

Objective: Perform RTL synthesis to generate a gate-level netlist.
Tasks:
• Import a Verilog RTL design (e.g., 4-bit adder).
• Set up Genus with a standard cell library and constraints (SDC file).
• Synthesize the design and generate a gate-level netlist.
• Analyze the synthesis report (area, timing).
Deliverables: Genus synthesis script, gate-level netlist, synthesis report.
Physical Design Concept: RTL-to-gate synthesis and timing constraints.

Experiment 2: Floorplanning in Cadence Innovus

Objective: Create a floorplan for a simple design.
Tasks:
• Import the synthesized netlist from Experiment 1 into Innovus.
• Define the core area, aspect ratio, and utilization.
• Place macros (if any) and create power rings.
• Save and verify the floorplan.
Deliverables: Floorplan database, Innovus script, floorplan screenshot.
Physical Design Concept: Floorplanning and power planning.

Experiment 3: Power Planning and Analysis

Objective: Implement and analyze power distribution in a design.
Tasks:
• Load the floorplan from Experiment 2 in Innovus.
• Add power stripes and vias for VDD/VSS.
• Perform IR drop analysis to check power integrity.
• Generate and analyze the IR drop report.
Deliverables: Innovus power plan script, IR drop report, power mesh screenshot.
Physical Design Concept: Power integrity and IR/EM analysis.
Experiment 4: Standard Cell Placement
Objective: Perform placement of standard cells in Innovus.
Tasks:
• Load the floorplanned design.
• Run placement with timing-driven optimization.
• Check placement quality (congestion, cell density).
• Save the placed design.
Deliverables: Innovus placement script, placement database, congestion map.
Physical Design Concept: Timing-driven placement and congestion analysis.

Experiment 5: Pre-CTS Timing Analysis

Objective: Perform static timing analysis (STA) before clock tree synthesis.
Tasks:
• Load the placed design in Innovus.
• Set up timing constraints (SDC) for a single clock.
• Run STA to check setup and hold times.
• Analyze timing reports and identify critical paths.
Deliverables: STA report, Innovus timing script, critical path analysis.
Physical Design Concept: Pre-CTS STA and timing path analysis.

Experiment 6: Clock Tree Synthesis (CTS)

Objective: Build a clock tree for a sequential design.
Tasks:
• Import a placed sequential design (e.g., 4-bit counter).
• Configure CTS parameters (skew, latency) in Innovus.
• Run CTS and analyze clock tree quality (skew, power).
• Save the CTS database.
Deliverables: CTS script, clock tree report, clock tree visualization.
Physical Design Concept: Clock tree synthesis and skew optimization.
Experiment 7: Post-CTS Timing Analysis
Objective: Perform STA after clock tree synthesis.
Tasks:
• Load the post-CTS design from Experiment 6.
• Update timing constraints to include clock tree effects.
• Run STA and check setup/hold violations.
• Compare pre-CTS and post-CTS timing reports.
Deliverables: Post-CTS STA report, Innovus script, timing comparison.
Physical Design Concept: Post-CTS timing analysis and optimization.

Experiment 8: Routing in Innovus

Objective: Perform global and detailed routing.
Tasks:
• Load the post-CTS design.
• Run global and detailed routing with timing-driven optimization.
• Check routing quality (congestion, DRC violations).
• Save the routed design.
Deliverables: Routing script, routed database, congestion/DRC report.
Physical Design Concept: Routing and congestion mitigation.

Experiment 9: Post-Route Optimization

Objective: Optimize timing and power after routing.
Tasks:
• Load the routed design in Innovus.
• Perform post-route optimization to fix timing violations (e.g., cell sizing, buffer
insertion).
• Re-run STA and analyze improvements.
• Generate final timing and power reports.
Deliverables: Optimization script, final STA report, power report.
Physical Design Concept: Post-route timing and power optimization.
Experiment 10: Design Rule Checking (DRC)
Objective: Perform physical verification for DRC.
Tasks:
• Export the routed design to GDSII format in Innovus.
• Use a DRC tool (e.g., Calibre or Innovus DRC) to check design rules.
• Analyze and fix DRC violations (e.g., spacing, width errors).
• Generate a clean DRC report.
Deliverables: DRC script, GDSII file, DRC report.
Physical Design Concept: Physical verification and DRC.

Experiment 11: Layout vs. Schematic (LVS) Verification

Objective: Verify layout consistency with the schematic.
Tasks:
• Load the GDSII and netlist in an LVS tool (e.g., Calibre).
• Run LVS to check for connectivity and device mismatches.
• Analyze and fix LVS errors.
• Generate a clean LVS report.
Deliverables: LVS script, LVS report, corrected GDSII (if needed).
Physical Design Concept: LVS verification and netlist consistency.

Experiment 12: Full Physical Design Flow for a Small Design

Objective: Implement a complete physical design flow for a small RTL design (e.g., traffic
light controller).
Tasks:
• Synthesize the RTL design in Genus.
• Perform floorplanning, placement, CTS, routing, and post-route optimization in
Innovus.
• Run STA, DRC, and LVS to verify the design.
• Generate final GDSII and timing/power reports.
Deliverables: Full flow scripts, GDSII, timing/power reports, DRC/LVS reports.
Physical Design Concept: End-to-end physical design flow integration.
12 SystemVerilog and UVM Experiments for B.Tech Students: Design Verification

Experiment 1: Introduction to SystemVerilog and Testbench Basics

Objective: Learn SystemVerilog syntax and create a basic testbench for a combinational
circuit.
Tasks:
• Write a SystemVerilog testbench for a 4-bit adder (from a previous Verilog
experiment).
• Use SystemVerilog features like logic data type and initial blocks.
• Simulate and verify the adder’s functionality.
Deliverables: SystemVerilog testbench, simulation waveforms.
Verification Concept: Basic testbench structure and stimulus generation.

Experiment 2: SystemVerilog Assertions for Combinational Logic

Objective: Use SystemVerilog assertions to verify a multiplexer.
Tasks:
• Write immediate and concurrent assertions for a 4:1 multiplexer.
• Create a testbench to drive inputs and check assertions.
• Simulate and observe assertion pass/fail conditions.
Deliverables: SystemVerilog code, testbench, simulation results.
Verification Concept: Assertion-based verification (ABV) and property checking.

Experiment 3: Randomization in SystemVerilog

Objective: Implement randomized testing for a 4-bit ALU.
Tasks:
• Write a SystemVerilog testbench using rand variables to generate random inputs for
an ALU.
• Use constraints to limit input ranges (e.g., valid operation codes).
• Simulate and verify ALU operations with random inputs.
Deliverables: SystemVerilog testbench, simulation waveforms.
Verification Concept: Random stimulus generation and constraint-driven testing.
Experiment 4: Coverage-Driven Verification
Objective: Implement functional coverage for a 4-bit counter.
Tasks:
• Write a SystemVerilog testbench with covergroups for a 4-bit up/down counter.
• Define coverpoints for counter states and transitions.
• Simulate and analyze coverage reports.
Deliverables: SystemVerilog testbench, coverage report, simulation results.
Verification Concept: Functional coverage and coverage analysis.

Experiment 5: SystemVerilog Classes and Object-Oriented Programming

Objective: Use SystemVerilog classes to create a modular testbench.
Tasks:
• Create a SystemVerilog class to model transactions for a 4:1 multiplexer.
• Write a testbench using the class to generate and drive transactions.
• Simulate and verify multiplexer behavior.
Deliverables: SystemVerilog code, testbench, simulation waveforms.
Verification Concept: Object-oriented programming (OOP) in verification.

Experiment 6: Interface Constructs in SystemVerilog

Objective: Use SystemVerilog interfaces to simplify testbench connections.
Tasks:
• Create a SystemVerilog interface for a DUT (e.g., 4-bit adder).
• Write a testbench using the interface to drive and monitor signals.
• Simulate and verify the design.
Deliverables: SystemVerilog interface, testbench, simulation results.
Verification Concept: Interface-based DUT connection and modularity.
Experiment 7: Introduction to UVM - Basic Testbench
Objective: Build a basic UVM testbench for a combinational circuit.
Tasks:
• Create a UVM testbench for a full adder with UVM components (driver, monitor,
scoreboard).
• Use UVM phases (build, connect, run).
• Simulate and verify the adder’s functionality.
Deliverables: UVM testbench code, simulation results.
Verification Concept: UVM testbench structure and phase-based execution.

Experiment 8: UVM Sequence and Sequencer

Objective: Implement UVM sequences to generate stimulus for a DUT.
Tasks:
• Write a UVM sequence to generate transactions for a 4:1 multiplexer.
• Connect the sequence to a sequencer and driver in a UVM testbench.
• Simulate and verify multiplexer behavior.
Deliverables: UVM testbench code, sequence code, simulation waveforms.
Verification Concept: UVM sequence generation and transaction handling.

Experiment 9: UVM Scoreboard and Functional Checking

Objective: Implement a UVM scoreboard to verify a 4-bit counter.
Tasks:
• Create a UVM testbench with a scoreboard to compare expected vs. actual counter
outputs.
• Use UVM analysis ports to collect DUT outputs.
• Simulate and verify counter functionality.
Deliverables: UVM testbench code, scoreboard, simulation results.
Verification Concept: Scoreboard-based verification and analysis ports.
Experiment 10: UVM Register Model
Objective: Implement a UVM register model for a simple DUT.
Tasks:
• Design a DUT with a few registers (e.g., a simple control register block).
• Create a UVM register model to verify register read/write operations.
• Simulate and verify register functionality using UVM testbench.
Deliverables: UVM testbench, register model, simulation results.
Verification Concept: Register abstraction layer (RAL) and register verification.

Experiment 11: Constrained Random Verification with UVM

Objective: Perform constrained random verification (CRV) for an ALU.
Tasks:
• Write a UVM testbench for an N-bit ALU with constrained random sequences.
• Use UVM coverage to track operation and input coverage.
• Simulate and analyze coverage and verification results.
Deliverables: UVM testbench, coverage report, simulation waveforms.
Verification Concept: Constrained random verification and coverage closure.

Experiment 12: UVM Testbench for a Traffic Light Controller

Objective: Develop a complete UVM testbench for a traffic light controller.
Tasks:
• Create a UVM testbench with driver, monitor, scoreboard, and sequences for a traffic
light controller FSM.
• Implement functional coverage for states and transitions.
• Simulate and verify the controller’s timing and state transitions.
Deliverables: UVM testbench code, coverage report, simulation results.
Verification Concept: System-level verification and UVM methodology integration.
12 Verilog Experiments for B.Tech Students: Verilog and RTL Design

Experiment 1: Introduction to Verilog and Basic Gates

Objective: Understand Verilog syntax and implement basic logic gates (AND, OR, NOT,
XOR).
Tasks:
• Write Verilog code for AND, OR, NOT, and XOR gates.
• Create a testbench to verify gate functionality.
• Simulate and observe waveforms.
Deliverables: Verilog code, testbench, simulation waveforms.
RTL Concept: Introduction to combinational logic and module instantiation.

Experiment 2: Combinational Logic - Half Adder and Full Adder

Objective: Design and verify combinational circuits using Verilog.
Tasks:
• Implement a half adder and full adder in Verilog (dataflow and behavioral modeling).
• Write a testbench to test all input combinations.
• Simulate and verify the truth table.
Deliverables: Verilog code, testbench, simulation results.
RTL Concept: Combinational logic design and dataflow modeling.

Experiment 3: 4-Bit Adder/Subtractor

Objective: Build a 4-bit adder/subtractor circuit using Verilog.
Tasks:
• Design a 4-bit ripple carry adder using full adder modules.
• Extend the design to perform subtraction using 2’s complement.
• Write a testbench to verify addition and subtraction.
Deliverables: Verilog code, testbench, simulation waveforms.
RTL Concept: Hierarchical design and module reuse.
Experiment 4: Multiplexer and Demultiplexer
Objective: Implement and verify 4:1 multiplexer and 1:4 demultiplexer.
Tasks:
• Write Verilog code for a 4:1 MUX and 1:4 DEMUX using behavioral modeling.
• Create a testbench to verify input-output combinations.
• Simulate and analyze timing.
Deliverables: Verilog code, testbench, simulation results.
RTL Concept: Conditional statements and combinational logic.

Experiment 5: Decoder and Encoder

Objective: Design a 3:8 decoder and 8:3 encoder in Verilog.
Tasks:
• Implement a 3:8 decoder and an 8:3 priority encoder.
• Write testbenches to verify functionality.
• Simulate and check output patterns.
Deliverables: Verilog code, testbench, simulation waveforms.
RTL Concept: Combinational logic and priority encoding.

Experiment 6: Flip-Flops (D, JK, T)

Objective: Understand sequential logic by implementing flip-flops.
Tasks:
• Write Verilog code for D, JK, and T flip-flops.
• Create a testbench to test edge-triggered behavior.
• Simulate and observe clock-driven outputs.
Deliverables: Verilog code, testbench, simulation results.
RTL Concept: Sequential logic and clocked circuits.

Experiment 7: 4-Bit Synchronous Counter

Objective: Design a 4-bit synchronous up/down counter.
Tasks:
• Implement a 4-bit counter with up/down control in Verilog.
• Write a testbench to verify counting sequences.
• Simulate and verify synchronous operation.
Deliverables: Verilog code, testbench, simulation waveforms.
RTL Concept: Synchronous sequential design and state transitions.
Experiment 8: Shift Register (SISO, SIPO)
Objective: Implement serial-in-serial-out (SISO) and serial-in-parallel-out (SIPO) shift
registers.
Tasks:
• Write Verilog code for 4-bit SISO and SIPO shift registers.
• Create a testbench to verify shifting operations.
• Simulate and observe data shifting.
Deliverables: Verilog code, testbench, simulation results.
RTL Concept: Sequential data storage and shifting.

Experiment 9: Finite State Machine - Sequence Detector

Objective: Design a Moore FSM to detect a specific sequence (e.g., 1011).
Tasks:
• Implement a Moore FSM in Verilog to detect the sequence 1011.
• Write a testbench to test sequence detection.
• Simulate and verify state transitions and outputs.
Deliverables: Verilog code, testbench, state diagram, simulation waveforms.
RTL Concept: Finite state machines and state encoding.

Experiment 10: Mealy FSM - Vending Machine Controller

Objective: Design a Mealy FSM for a simple vending machine controller.
Tasks:
• Implement a Mealy FSM in Verilog for a vending machine (e.g., accepts coins,
dispenses product).
• Write a testbench to simulate coin inputs and product dispensing.
• Simulate and verify state transitions.
Deliverables: Verilog code, testbench, state diagram, simulation results.
RTL Concept: Mealy FSM and input-dependent outputs.
Experiment 11: Parameterized N-Bit ALU
Objective: Design a parameterized N-bit Arithmetic Logic Unit (ALU).
Tasks:
• Implement an ALU with operations like ADD, SUB, AND, OR, and XOR using
parameters for bit-width.
• Write a testbench to verify all operations.
• Simulate and analyze results for different bit-widths (e.g., 4-bit, 8-bit).
Deliverables: Verilog code, testbench, simulation waveforms.
RTL Concept: Parameterized design and modular arithmetic.

Experiment 12: Traffic Light Controller

Objective: Design a complete traffic light controller using Verilog.
Tasks:
• Implement a traffic light controller FSM with states for Red, Green, and Yellow
lights.
• Include timing control (e.g., using a counter for delays).
• Write a testbench to simulate traffic light sequences.
• Simulate and verify timing and state transitions.
Deliverables: Verilog code, testbench, state diagram, simulation results.
RTL Concept: System-level design, timing control, and FSM integration.