INTEGRATED SYSTEM DESIGN

AUTOMATION
22SDEC10R

STUDENT ID: ACADEMIC YEAR: 2023-24

STUDENT NAME:
 Table of Contents

1. Session 01: Introductory Session ............................................................................ NA

2. Session 02: Construct layout of a combinational logic design (minimum 8
transistors) using Cadence Layout XL/ GXL environment with zero design rule
check (DRC) and LVS errors...................................................................................... 1
3. Session 03: Extract parasitic components of the designed combinational logic
(minimum 8 transistors) using QRC extraction tool of cadence and perform post-
layout simulation ......................................................................................................... 5
4. Session 04: Analyze the effect of parasitic capacitance/resistances on post layout
simulation of combinational logic circuits. .............................................................. 10
5. Session 05: Construct layout of two different cells and call those layouts to
construct layout of a third cell comprising of those two cells. .............................. 14
6. Session 06: Design a SR latch and call the latch to design a SR flipflop using
Verilog HDL in cadence digital environment (nclaunch). .................................... 18
7. Session 07: Extract RTL of counter logic after synthesis and report area, timing,
power dissipated by the design (use genus tool). .................................................... 23
8. Session 08: Design layout of counter logic using innovus tool and report post-
layout area, timing, power of the design. Compare with the pre layout results. 27
9. Session 09: Undergo timing analysis of counter logic using innovus and check for
set-up and hold time violations. Save and Export the design for tape out.
10. Session 10: Interface FPGA with XILINX digital design environment to
implement the counter logic into the FPGA .......................................................... 32
11. Session 11: Construct a FSM with Verilog and undergo simulation and
subsequent synthesis using nclaunch and genus tool of cadence. ......................... 47
12. Session 12: Undergo spice simulation of combinational circuits (minimum 10
transistors) using LTSpice and undergo transient analysis. ................................. 51
13. Session 13: Undergo spice simulation of sequential circuits (minimum 10
transistors) using LT Spice and undergo transient analysis. ................................ 55

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 A.Y. 2023-24 LAB/SKILL CONTINUOUS EVALUATION
S.No Date Experiment Name Pre- In-Lab (25M) Post- Viva Total Faculty
Lab Program/ Data Analysis Lab Voce (50M) Signature
(10M) Procedure and & (10M) (5M)
(5M) Results Inference
(10M) (10M)
1. Introductory Session -NA-
Construct layout of a
combinational logic design
(minimum 8 transistors) using
2.
Cadence Layout XL/ GXL
environment with zero design rule
check (DRC) and LVS errors.
Extract parasitic components of
the designed combinational logic
(minimum 8 transistors) using
3.
QRC extraction tool of cadence
and perform post-layout
simulation.
Analyze the effect of parasitic
capacitance/resistances on post
4.
layout simulation of combinational
logic circuits.
Construct layout of two different
cells and call those layouts to
5.
construct layout of a third cell
comprising of those two cells.
Design a SR latch and call the latch
6. to design a SR flipflop using
Verilog HDL in cadence digital

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S.No Date Experiment Name Pre- In-Lab (25M) Post- Viva Total Faculty
Lab Program/ Data Analysis Lab Voce (50M) Signature
(10M) Procedure and & (10M) (5M)
(5M) Results Inference
(10M) (10M)
environment (nclaunch).

Extract RTL of counter logic after

synthesis and report area, timing,
7.
power dissipated by the design (use
genus tool).
Design layout of counter logic
using innovus tool and report post-
8. layout area, timing, power of the
design. Compare with the pre
layout results
Undergo timing analysis of counter
logic using innovus and check for
9. set-up and hold time violations.
Save and Export the design for
tape out.
Interface FPGA with XILINX
digital design environment to
10.
implement the counter logic into
the FPGA.
Construct a FSM with Verilog and
undergo simulation and
11.
subsequent synthesis using
nclaunch and genus tool of cadence
S.No Date Experiment Name Pre- In-Lab (25M) Post- Viva Total Faculty
Lab Program/ Data Analysis Lab Voce (50M) Signature
(10M) Procedure and & (10M) (5M)
(5M) Results Inference
(10M) (10M)
Undergo spice simulation of
combinational circuits (minimum
12
10 transistors) using LTSpice and
undergo transient analysis.
Design and undergo transient
analysis of basic logic gates using
13. Transmission Gate Logic. Analyze
the results with respect to the logic
obtained from PTL logic.
Experiment <TO BE FILLED BY STUDENT> Student ID <TO BE FILLED BY STUDENT>
Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

Exp No.1: Construct layout of a combinational logic design (minimum 8 transistors)

using Cadence Layout XL/ GXL environment with zero design rule check (DRC) and
LVS errors
Aim/Objective:
The aim of this experiment is to construct layout of a combinational logic design (minimum 8
transistors) using Cadence Layout XL/ GXL environment with zero design rule check (DRC)
and LVS errors.

Prerequisites
- Basic understanding of CMOS technology and combinational logic.
- Familiarity with Cadence Virtuoso environment.
- Completed tutorials on Cadence schematic and layout editor basics.

Software
- Cadence Virtuoso Schematic Editor
- Cadence Virtuoso Layout XL/GXL
- Design Rule Checking (DRC) tool
- Layout Versus Schematic (LVS) tool

Procedure
The course starts with understanding the flow of VLSI Full custom design. The full custom
flow will be executed using 90 and 45 nm technologies in CADENCE analog design
environment. The hierarchy of steps that will be followed in full custom design will be as
follows:
(a) Design of schematic in transistor level using CADENCE schematic window. The
schematic will consist of electrical components like MOSFETs, resistances,
capacitances, connecting wires, ports etc. No electrical sources should be connected in
the schematic window.
(b) A symbol mapping that particular schematic should be designed in CADENCE analog
symbol window. It should be noted that the symbol will represent the schematic at the
top level. Hence the symbol input/output pin names should match with the
corresponding port names in the schematic. If it does-not match, the tool will show
warning in the CIW window. If any modifications made in schematic, the
corresponding symbol should again be updated with the modifications. All
modifications in any windows of cadence should be followed by the check and save
option.
(c) Verification of functionality of that corresponding schematic/symbol can be
performed using a new schematic called test circuit where the symbol will be called
and that symbol will be connected to sources and other electrical components for
simulation.

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(d) Layout of the schematic will be performed using layout XL/GXL extension in ADE
environment. The details of steps should be followed from shared cadence manual.
After design of Layout, the layout properties will be mapped with the design rules
using DRC steps of cadence (follow manual). After correcting all errors, layout will
be matched with the corresponding schematic using LVS check steps of cadence

References
- Cadence Virtuoso Layout Editor User Guide
- CMOS VLSI Design: A Circuits and Systems Perspective by Neil H. E. Weste and David
Money Harris

Pre-Lab:
1. Discuss some of the design rules followed for designing VLSI circuits.

2. Discuss the necessities of DRC and LVS check in VLSI.

In-Lab:
• Circuit (Schematic):

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• Circuit (Layout) (Add coloured image):

• Analysis and Inferences:

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Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

Sample VIVA-VOCE Questions (In-Lab):

1. Discuss some of the errors encountered during DRC check in VLSI.

2. What are the reasons of having a LVS mismatch though you have DRC clean layout.

Post-Lab:
1. To correct DRC and LVS errors encountered during design
• Results:

• Analysis and Inferences:

Evaluator Remark (if Any):

Marks Secured: _____out of 50

Signature of the Evaluator with Date

Evaluator MUST ask Viva-voce prior to signing and posting marks for each experiment.

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Experiment <TO BE FILLED BY STUDENT> Student ID <TO BE FILLED BY STUDENT>
Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

Exp no 2: Extract parasitic components of the designed combinational logic (minimum

8 transistors) using QRC extraction tool of cadence and perform post-layout simulation

Aim: To extract parasitic components from a combinational logic circuit with a minimum of
8 transistors using the Cadence Quantus QRC Extraction Tool and perform post-layout
simulation to analyze the effects of these parasitics on circuit performance.

Prerequisites

- Understanding of CMOS technology and combinational logic circuits.

- Familiarity with Cadence Virtuoso for schematic and layout creation.
- Knowledge of parasitic components and their impact on circuit performance.
- Completion of previous labs on basic schematic and layout creation in Cadence.

Software and Tools

- Cadence Virtuoso Schematic Editor

- Cadence Virtuoso Layout XL/GXL
- Cadence Quantus QRC Extraction Tool
- Cadence Spectre for simulation

Procedure

I. Extracting Parasitic Components Using QRC

1. Open QRC Tool:
- From the Cadence environment, launch the Quantus QRC Extraction Tool.

2. Set Up Extraction:
- Load the layout of your combinational logic circuit.
- Configure extraction settings for parasitic resistance and capacitance.
- Choose appropriate extraction options based on your technology library.

3. Run Extraction:
- Execute the extraction process.
- Save the extracted parasitic components to a file (usually a `.spef` or similar file format).

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II. Performing Post-Layout Simulation

1. Prepare Simulation Setup:
- Open Cadence Virtuoso ADE (Analog Design Environment).
- Load the schematic of your combinational logic circuit.
- Include the extracted parasitic file in the simulation setup.

2. Configure Simulation:
- Set up the testbench with appropriate stimulus for the inputs.
- Configure simulation parameters (e.g., transient analysis).

3. Run Simulation:
- Perform the post-layout simulation with parasitics included.
- Analyze the results, focusing on the impact of parasitics on performance metrics such as
delay, power, and signal integrity.

IV. Analysis and Verification

1. Compare Results:
- Compare pre-layout and post-layout simulation results.
- Identify the impact of parasitics on circuit performance.

2. Document Findings:
- Summarize the key differences observed in the simulations.
- Provide insights into how parasitics affect the combinational logic circuit.

Prelab Questions

1. What are parasitic components in a circuit layout?

2. Why is it important to extract parasitic components for post-layout simulation?

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In-Lab:
• Circuit (Schematic):

• Circuit (Layout) (Add coloured image):

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Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

• Analysis and Inferences:

Viva Questions

1. Explain the process of parasitic extraction in Cadence QRC.

2. How do parasitic resistances and capacitances affect the performance of a combinational

logic circuit?

3. What are the typical steps involved in post-layout simulation?

References

- Cadence Virtuoso Layout Editor User Guide

- Cadence Quantus QRC Extraction Tool User Guide
- CMOS VLSI Design: A Circuits and Systems Perspective by Neil H. E. Weste and David
Money Harris
- Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey

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Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

Post-Lab:
1. To correct QRC errors encountered during design
• Results:

• Analysis and Inferences:

Evaluator Remark (if Any):

Marks Secured: _____out of 50

Signature of the Evaluator with Date

Evaluator MUST ask Viva-voce prior to signing and posting marks for each experiment.

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Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

Exp no 3: Analyse the effect of parasitic capacitance/resistances on post layout

simulation of combinational logic circuits
Aim:

To analyze the effects of parasitic capacitance and resistance on the performance of

combinational logic circuits using post-layout simulation.

Prerequisites

- Basic knowledge of CMOS technology and combinational logic circuits.

- Familiarity with Cadence Virtuoso for schematic and layout creation.
- Understanding of parasitic components and their impact on circuit performance.
- Completion of previous labs involving basic schematic and layout creation in Cadence.

Software and Tools

- Cadence Virtuoso Schematic Editor

- Cadence Virtuoso Layout XL/GXL
- Cadence Quantus QRC Extraction Tool
- Cadence Spectre for simulation

Procedure

(a) Layout of the schematic will be performed using layout XL/GXL extension in ADE
environment. The details of steps should be followed from shared cadence manual. After
design of Layout, the layout properties will be mapped with the design rules using DRC
steps of cadence (follow manual). After correcting all errors, layout will be matched with
the corresponding schematic using LVS check steps of cadence

(b) Next, you have to do RC extraction of the DRC/LVS clean design using QRC tool of
cadence. Follow the steps from cadence manual for RC extraction of the circuit. After
successful RC extraction you will see the av_extracted view attached to the schematic of the
design.

(c) Next, a configuration (config) file has to be mapped to the test circuit of the
corresponding schematic that will help mapping the parasitic components to the test circuit of
the designs.

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Prelab Questions

1. What are parasitic components in a circuit layout?

2. Why is it important to extract parasitic components for post-layout simulation?

In-Lab:
• Circuit (Schematic):

• Circuit (Layout) (Add coloured image):

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Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

• Analysis and Inferences:

Viva Questions

1. Explain the process of parasitic extraction in Cadence QRC.

2. How do parasitic resistances and capacitances affect the performance of a VLSI Design.

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Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

References

- Cadence Virtuoso Layout Editor User Guide

- Cadence Quantus QRC Extraction Tool User Guide
- CMOS VLSI Design: A Circuits and Systems Perspective by Neil H. E. Weste and David
Money Harris
- Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey

Post-Lab:
1. To correct QRC errors encountered during design and compare pre layout with post
layout results.

• Results:

• Analysis and Inferences:

Evaluator Remark (if Any):

Marks Secured: _____out of 50

Signature of the Evaluator with Date

Evaluator MUST ask Viva-voce prior to signing and posting marks for each experiment.

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Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

EXP 4: Construct layout of two different cells and call those layouts to construct layout
of a third cell comprising of those two cells

Aim

To construct the layout of two different cells and use those layouts to create a third cell
comprising the first two cells, demonstrating hierarchical design in Cadence Virtuoso.

Prerequisites

- Understanding of CMOS technology and VLSI design principles.

- Familiarity with Cadence Virtuoso for schematic and layout creation.
- Knowledge of hierarchical design concepts in VLSI.

Software and Tools

- Cadence Virtuoso Schematic Editor

- Cadence Virtuoso Layout XL/GXL
- Design Rule Checking (DRC) tool
- Layout Versus Schematic (LVS) tool

Procedure

It is possible to perform post layout simulation of a module comprising of submodules that

has error free layouts. It should be noted that the submodules should be DRC/LVS clean and
QRC extracted. A config. file need to be attached to the top module which comproses of
submodule. This will help to incorporate all extracted parasitics of the submodules for
simulation. It is instructed to follow the cadence steps provided in manual for operation.

Prelab Questions

1. What are the benefits of using hierarchical design in VLSI?

2. How do DRC and LVS checks help ensure the correctness of a VLSI layout?
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3. Explain the process of instantiating a cell within another cell in Cadence Virtuoso.

In-Lab:
• Circuit (Schematic):

• Circuit (Layout) (Add coloured image):

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Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

• Analysis and Inferences:

Viva Questions

1. Explain the process of parasitic extraction in Cadence QRC and the calling of those
parasitics in top modules for verification

2. How do parasitic resistances and capacitances affect the performance of a VLSI Design.

References

- Cadence Virtuoso Layout Editor User Guide

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Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

- Cadence Quantus QRC Extraction Tool User Guide

- CMOS VLSI Design: A Circuits and Systems Perspective by Neil H. E. Weste and David
Money Harris
- Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey

Post-Lab:
1. To execute post layout simulation of a top module by calling RC-extracted layout of
submodules for VLSI analog circuits.

• Results:

• Analysis and Inferences:

Evaluator Remark (if Any):

Marks Secured: _____out of 50

Signature of the Evaluator with Date

Evaluator MUST ask Viva-voce prior to signing and posting marks for each experiment

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Experiment <TO BE FILLED BY STUDENT> Student ID <TO BE FILLED BY STUDENT>
Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

EXP no: 5

Design a SR latch and call the latch to design a SR flipflop using Verilog HDL in
cadence digital environment (nclaunch).
Aim

To design an SR latch and use it to design an SR flip-flop using Verilog HDL in the Cadence
digital environment (nclaunch).

Prerequisites

- Basic understanding of digital logic design and flip-flops.

- Familiarity with Verilog HDL and its syntax.
- Knowledge of Cadence digital design tools, specifically nclaunch.

Software and Tools

- Cadence Virtuoso Schematic Editor

- Cadence nclaunch (Cadence Incisive Unified Simulator)
- Verilog HDL

Procedure

I. Design an SR Latch in Verilog

1. Open Cadence Environment:
- Launch Cadence Virtuoso and navigate to the digital design environment (nclaunch).

2. Create a New Verilog File for SR Latch:

- In the Cadence nclaunch environment, create a new Verilog file for the SR latch.
- Write the Verilog code for the SR latch

3. Save and Compile the Verilog Code:

- Save the Verilog file.
- Compile the Verilog code to check for syntax errors.

II. Design an SR Flip-Flop Using the SR Latch

1. Create a New Verilog File for SR Flip-Flop:
- In the Cadence nclaunch environment, create a new Verilog file for the SR flip-flop.

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- Write the Verilog code for the SR flip-flop using the SR latch module

2. Save and Compile the Verilog Code:

- Save the Verilog file.
- Compile the Verilog code to check for syntax errors.

III. Simulate the SR Flip-Flop

1. Create a Testbench:
- Create a new Verilog file for the testbench.
- Write the testbench code to simulate the SR flip-flop.
2. Run the Simulation:
- Load the testbench in the Cadence nclaunch environment.
- Run the simulation and observe the waveforms to verify the functionality of the SR flip-
flop.

IV. Analysis and Verification

1. Analyze Waveforms:
- Use the waveform viewer to analyze the output of the SR flip-flop.
- Ensure the SR flip-flop operates as expected according to the truth table.

2. Document Findings:
- Document the results of the simulation, including screenshots of waveforms and a
summary of the behavior observed.

Prelab Questions

1. What is the difference between an SR latch and an SR flip-flop?

2. Why do we use clock signals in flip-flops?

In-Lab:
• Verilog code along with test bench:

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• NC Launch simulator results (waveforms):

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• Analysis and Inferences:

Viva Questions

1. What is meant by elaborate design in vlsi semi custom flow.

2. Explain the hierarchical steps in cadence digital environment followed for simulation
using nclaunch.

References

- Cadence Virtuoso User Guide

- Digital Design and Computer Architecture by David Harris and Sarah Harris
- Verilog HDL by Samir Palnitkar
- Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey

Post-Lab:
1. To design a top modules while calling submodules for VLSI digital design using
nclaunch.

• Code and Waveform:

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Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

• Analysis and Inferences:

Evaluator Remark (if Any):

Marks Secured: _____out of 50

Signature of the Evaluator with Date

Evaluator MUST ask Viva-voce prior to signing and posting marks for each experiment

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Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

Exp no: 6

Extract RTL of counter logic after synthesis and report area, timing, power dissipated
by the design (use genus tool).

Aim

To extract the RTL of a counter logic circuit after synthesis and report the area, timing, and
power dissipation using the Cadence Genus tool.

Prerequisites

- Basic understanding of digital logic design and counters.

- Familiarity with Verilog HDL for designing digital circuits.
- Knowledge of synthesis concepts and related metrics (area, timing, power).
- Familiarity with Cadence Genus tool for synthesis and analysis.

Software and Tools

- Cadence Genus Synthesis Solution

- Verilog HDL
- Text editor for writing and editing Verilog code

Procedure

$ source /home/install/cshrc
Welcome to Cadence tools Suite
$ genus
@genus:root: 1> read_libs /home/install/FOUNDRY/digital/90nm/dig/lib/slow.lib
@genus:root: 2> read_hdl counter.v
@genus:root: 3> elaborate
@genus:root: 4> read_sdc constraints_top.sdc
@genus:root: 5> gedit constraints_top.sdc
@genus:root: 6> read_sdc constraints_top.sdc
@genus:root: 7> syn_generic
@genus:root: 8> syn_map
@genus:root: 9> syn_opt
@genus:root: 10> report_power
@genus:root: 11> report_power > counter_power.repo
@genus:root: 12> report_power > counter_power.report

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@genus:root: 13> report_area

@genus:root: 14> report_area > counter_area.report
@genus:root: 15> report_timing
@genus:root: 16> report_timing > counter_timing.report
@genus:root: 17> write_hdl > counter_netlist.v
@genus:root: 18> write_sdc > counter_sdc.sdc
@genus:root: 19> synthesize -to_mapped -effort medium
@genus:root: 20> write_hdl > counter_netlist.v
@genus:root: 21> write_sdc > counter_sdc.sdc
@genus:root: 22> gui_show

Results

Document the Findings:

- Summarize the area, timing, and power dissipation of the counter design.
- Include relevant excerpts and screenshots from the reports in your documentation.

Prelab Questions

1. What is the purpose of synthesis in digital design?

2. How does the synthesis process affect the area, timing, and power of a digital

circuit?

3. Describe the function of a 4-bit binary counter.

Results: (Power timing and delay results post synthesis)

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RTL Design:

Viva Questions

1. Explain the steps involved in the synthesis process using Cadence Genus.

2. How do you interpret the area report generated after synthesis?

3. What are the key factors that affect the timing performance of a digital circuit?

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4. How can power dissipation be minimized in a synthesized design?

References

- Cadence Genus Synthesis Solution User Guide

- Digital Design and Computer Architecture by David Harris and Sarah Harris
- Verilog HDL by Samir Palnitkar
- CMOS VLSI Design: A Circuits and Systems Perspective by Neil H. E. Weste and David
Money Harris

• Analysis and Inferences:

Evaluator Remark (if Any):

Marks Secured: _____out of 50

Signature of the Evaluator with Date

Evaluator MUST ask Viva-voce prior to signing and posting marks for each experiment

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Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

Exp no : 7

Design layout of counter logic using innovus tool and report post-layout area, timing,
power of the design. Compare with the pre layout results.

Aim

To design the layout of a counter logic circuit using the Cadence Innovus tool and
report the post-layout area, timing, and power. Compare these results with the pre-
layout synthesis results.

Prerequisites

- Basic understanding of digital logic design and counters.

- Familiarity with Verilog HDL for designing digital circuits.
- Knowledge of synthesis, place and route, and related metrics (area, timing, power).
- Familiarity with Cadence Genus for synthesis and Cadence Innovus for place and route.

Procedure

We need to invoke innovus tool for digital layout design of the logic circuits. The detailed

steps of layout design can be found in cadence manual provided.

Prelab Questions

1. What is the purpose of synthesis and place and route in digital design?

2. How does the synthesis process differ from the place and route process?

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3. Describe the function of a 4-bit binary counter.

In Lab: (Layout Design)

Post Layout Results:

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Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

Viva Questions

1. Explain the steps involved in the synthesis process using Cadence Genus.

2. How does place and route impact the area, timing, and power of a digital circuit?

3. What are the typical challenges encountered during the place and route process?

4. How can post-layout optimization improve the design performance?

---

References

- Cadence Genus Synthesis Solution User Guide

- Cadence Innovus Implementation System User Guide

- Digital Design and Computer Architecture by David Harris and Sarah Harris

- Verilog HDL by Samir Palnitkar

- CMOS VLSI Design: A Circuits and Systems Perspective by Neil H. E. Weste and

David Money Harris

Post-Lab:

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Experiment <TO BE FILLED BY STUDENT> Student ID <TO BE FILLED BY STUDENT>
Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

2. To design layout of top modules while calling submodules for VLSI digital design
using nclaunch.

• Layout:

• Analysis and Inferences:

Viva Questions

5. Explain the steps involved in the synthesis process using Cadence Genus.

6. How does place and route impact the area, timing, and power of a digital circuit?

30
Experiment <TO BE FILLED BY STUDENT> Student ID <TO BE FILLED BY STUDENT>
Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

7. What are the typical challenges encountered during the place and route process?

8. How can post-layout optimization improve the design performance?

Evaluator Remark (if Any):

Marks Secured: _____out of 50

Signature of the Evaluator with Date

Evaluator MUST ask Viva-voce prior to signing and posting marks for each experiment

31
Experiment <TO BE FILLED BY STUDENT> Student ID <TO BE FILLED BY STUDENT>
Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

Exp no : 8

Undergo timing analysis of counter logic using innovus and check for set-up and hold

time violations. Save and Export the design for tape out.

Aim

Undergo timing analysis of counter logic using innovus and check for set-up and hold

time violations. Save and Export the design for tape out.

Prerequisites

- Basic understanding of digital logic design and flip-flops.

- Familiarity with Verilog HDL and its syntax.
- Knowledge of Cadence digital design tools, specifically nclaunch.

Software and Tools

- Cadence Virtuoso Schematic Editor

- Cadence nclaunch (Cadence Incisive Unified Simulator)
- Verilog HDL

Procedure

Timing analysis after layout using Cadence Innovus involves several detailed steps to ensure
that the design meets its timing requirements. Here is a step-by-step guide:

### 1. Setup Environment

Before starting the timing analysis, ensure that the environment is correctly set up:

- Load the necessary modules for Innovus.

- Set up the design environment, including the technology files, standard cell libraries, and
other necessary files.

### 2. Load Design

Load your design into Innovus:
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Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

```shell
innovus -files my_design.enc
```

Or within the Innovus GUI, you can open your design using the appropriate commands or
menu options.

### 3. Perform Floorplanning and Placement

Ensure that floorplanning and placement have been completed:

- **Floorplanning**: Define the placement of macros, IO pads, and power grid.

- **Placement**: Place standard cells in the defined floorplan.

Commands might include:

```shell
floorPlan ...
placeDesign ...
```

### 4. Perform Clock Tree Synthesis (CTS)

Synthesize the clock tree to balance the clock distribution across the design:

```shell
createClockTreeSpec ...
optDesign -cts ...
```

### 5. Perform Routing

Route the design to connect all the cells and blocks as per the netlist:

```shell
routeDesign ...
```

### 6. Extract Parasitics

Extract the parasitics (resistance and capacitance) from the routed design. This step is crucial
for accurate timing analysis:

```shell
extractRC ...
```

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Experiment <TO BE FILLED BY STUDENT> Student ID <TO BE FILLED BY STUDENT>
Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

### 7. Setup Timing Analysis

Set up the timing analysis environment, including specifying constraints and loading timing
libraries:

- **Constraints**: Load the design constraints (SDC file).

- **Libraries**: Load the necessary timing libraries (liberty files).

Commands might include:

```shell
set_analysis_view ...
read_sdc my_constraints.sdc
read_liberty -min my_library_min.lib
read_liberty -max my_library_max.lib
```

### 8. Perform Static Timing Analysis (STA)

Run static timing analysis to verify the timing of the design:

```shell
timeDesign -preCts
timeDesign -postCts
timeDesign -postRoute
```

These commands analyze the timing at different stages of the design flow. Typically, you
would check the timing at each stage to ensure that the design meets timing requirements
before moving on to the next stage.

### 9. Review Timing Reports

Analyze the timing reports generated by the `timeDesign` command:

- **Setup Analysis**: Check for setup timing violations.

- **Hold Analysis**: Check for hold timing violations.
- **Slack**: Ensure that all timing paths have positive slack.

### 10. Optimize Design

If there are timing violations, perform timing optimization:

- **Resynthesis**: Resynthesize critical paths.

- **Buffer Insertion**: Insert buffers to meet hold timing.
- **Sizing**: Resize cells to meet timing requirements.

Commands might include:

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Experiment <TO BE FILLED BY STUDENT> Student ID <TO BE FILLED BY STUDENT>
Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

```shell
optDesign ...
```

### 11. Iterative Analysis

Repeat the timing analysis and optimization steps iteratively until all timing requirements are
met.

### 12. Final Verification

Once timing is clean:

- Verify that all setup and hold violations are resolved.

- Perform a final parasitic extraction and timing analysis.
- Generate final timing reports for documentation.

### Example Commands for Final Steps

```shell
extractRC
timeDesign -postRoute
report_timing -max_paths 10
report_timing -hold -max_paths 10
```

### 13. Save and Export

Save the final design and export the necessary files for tape-out:

```shell
saveDesign my_final_design.enc
write_sdf my_final_design.sdf
write_def my_final_design.def
```

This guide outlines the critical steps for performing timing analysis after layout using
Cadence Innovus. The exact commands and flow may vary based on your design and project
requirements.

Prelab Questions

1. What is Static Timing Analysis (STA)?

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Experiment <TO BE FILLED BY STUDENT> Student ID <TO BE FILLED BY STUDENT>
Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

2. What are setup and hold times?

In-Lab:
• Layout design with timing analysis

36
Experiment <TO BE FILLED BY STUDENT> Student ID <TO BE FILLED BY STUDENT>
Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

• Analysis and Inferences:

Viva Questions

1. What is meant by elaborate design in vlsi semi custom flow.

2. Explain the hierarchical steps in cadence digital environment followed for simulation
using nclaunch.

37
Experiment <TO BE FILLED BY STUDENT> Student ID <TO BE FILLED BY STUDENT>
Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

References

- Cadence Virtuoso User Guide

- Digital Design and Computer Architecture by David Harris and Sarah Harris
- Verilog HDL by Samir Palnitkar
- Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey

Post-Lab:
3. T,iming violations in digital circuits

• Code and Waveform:

• Analysis and Inferences:

Evaluator Remark (if Any):

Marks Secured: _____out of 50

Signature of the Evaluator with Date

Evaluator MUST ask Viva-voce prior to signing and posting marks for each experiment
38
Experiment <TO BE FILLED BY STUDENT> Student ID <TO BE FILLED BY STUDENT>
Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

Exp no : 9

Interface FPGA with XILINX digital design environment to implement the counter logic into the

FPGA.

Aim

Interface FPGA with XILINX digital design environment to implement the counter logic into the

FPGA.

Prerequisites

Understanding the Application Requirements

Digital flow using XILINX

Software and Tools

XILINX VIVADO

Procedure

Implementing logic circuits on an FPGA using Xilinx tools involves several key steps, from
initial design to final hardware testing. Below is a detailed guide using Xilinx Vivado, which
is the current standard tool from Xilinx for FPGA development.

### Step-by-Step Guide for FPGA Implementation using Xilinx Vivado

#### 1. **Install Vivado Design Suite**

- **Download and Install**: Download the latest version of Vivado from the Xilinx website
and install it on your computer.
- **Licensing**: Obtain the necessary licenses for the features and devices you will be using.

#### 2. **Create a New Project**

- **Open Vivado**: Launch the Vivado Design Suite.
- **Create New Project**: Go to File > New Project, and follow the wizard.
- **Project Name and Location**: Specify the project name and directory.
- **Project Type**: Select RTL Project.
- **Add Sources**: Add existing HDL files or create new ones.
- **Add Constraints**: Add XDC constraint files if available (you can add them later as
well).
- **Select Device**: Choose the FPGA part or board you are targeting.

39
Experiment <TO BE FILLED BY STUDENT> Student ID <TO BE FILLED BY STUDENT>
Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

#### 3. **Design Entry**

- **Create HDL Code**: Write your logic circuit in VHDL or Verilog. Ensure your top
module matches the design's I/O requirements.
- **Add Source Files**: Add your HDL files to the project.
- Example (Verilog):
```verilog
module top_module (
input wire clk,
input wire reset,
input wire [3:0] a,
input wire [3:0] b,
output wire [7:0] result
);
// Your logic here
endmodule
```

#### 4. **Add Constraints**

- **XDC File**: Create or modify the constraints file (XDC). This file specifies pin
assignments and timing constraints.
- Example (XDC):
```tcl
set_property PACKAGE_PIN W5 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
```

#### 5. **Synthesize Design**

- **Run Synthesis**: Click on the "Run Synthesis" button in the Flow Navigator.
- **Check Reports**: Review the synthesis reports for any errors or warnings.

#### 6. **Implement Design**

- **Run Implementation**: Click on the "Run Implementation" button.
- **Check Timing**: Review the timing summary to ensure your design meets timing
constraints.

#### 7. **Generate Bitstream**

- **Run Bitstream Generation**: Click on the "Generate Bitstream" button.
- **Review**: Ensure that the bitstream generation completes successfully.

#### 8. **Program the FPGA**

- **Open Hardware Manager**: Open the Hardware Manager from Vivado.

40
Experiment <TO BE FILLED BY STUDENT> Student ID <TO BE FILLED BY STUDENT>
Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

- **Connect to FPGA**: Connect your FPGA development board to your computer via USB
and power it on.
- **Auto Connect**: Click on "Open Target" and select "Auto Connect".
- **Program Device**: Click on the "Program Device" button and select the generated
bitstream file (.bit).

#### 9. **Verify the Design**

- **Testing**: Verify the functionality of your design on the hardware. Use test inputs and
observe outputs using onboard LEDs, serial communication, or other peripherals.
- **Debugging**: If there are issues, use Vivado’s debugging tools such as ILA (Integrated
Logic Analyzer) and VIO (Virtual Input/Output) to diagnose and fix problems.

#### 10. **Iterate and Optimize**

- **Modify Design**: Based on testing and debugging, make necessary modifications to
your HDL code or constraints.
- **Re-synthesize**: Repeat the synthesis, implementation, and bitstream generation steps as
needed.

### Additional Tips

- **Simulate Before Synthesis**: Use the Vivado simulator to verify the logic functionality
before running synthesis.
- **Use IP Cores**: Take advantage of Xilinx IP cores for common functions like FIFOs,
DSP blocks, memory controllers, etc.
- **Documentation and Version Control**: Keep detailed documentation of your design and
use version control systems like Git to manage your source files.

By following these steps, you can successfully implement logic circuits on an FPGA using
the Xilinx Vivado Design Suite.

Prelab Questions

1. What is a bitstream in FPGA design?

2. How do you optimize an FPGA design?

41
Experiment <TO BE FILLED BY STUDENT> Student ID <TO BE FILLED BY STUDENT>
Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

In-Lab:
• FPGA Implementation

42
Experiment <TO BE FILLED BY STUDENT> Student ID <TO BE FILLED BY STUDENT>
Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

• Analysis and Inferences:

Viva Questions

1. What is meant by elaborate design in vlsi semi custom flow.

2. Explain the hierarchical steps in cadence digital environment followed for simulation
using nclaunch.

References

- Cadence Virtuoso User Guide

- Digital Design and Computer Architecture by David Harris and Sarah Harris
- Verilog HDL by Samir Palnitkar
- Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey

43
Experiment <TO BE FILLED BY STUDENT> Student ID <TO BE FILLED BY STUDENT>
Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

Post-Lab:
4. T,iming violations in digital circuits

• Code and Waveform:

• Analysis and Inferences:

Evaluator Remark (if Any):

Marks Secured: _____out of 50

Signature of the Evaluator with Date

Evaluator MUST ask Viva-voce prior to signing and posting marks for each experiment

44
Experiment <TO BE FILLED BY STUDENT> Student ID <TO BE FILLED BY STUDENT>
Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

Exp no : 10

Construct a FSM with Verilog and undergo simulation and subsequent synthesis using nclaunch and

genus tool of cadence

Aim

Construct a FSM with Verilog and undergo simulation and subsequent synthesis using nclaunch and

genus tool of cadence

Prerequisites

Understanding the Application Requirements

Digital flow using XILINX

Software and Tools

XILINX VIVADO

Procedure

Implementing logic circuits on an FPGA using Xilinx tools involves several key steps, from
initial design to final hardware testing. Below is a detailed guide using Xilinx Vivado, which
is the current standard tool from Xilinx for FPGA development.

### Step-by-Step Guide for FPGA Implementation using Xilinx Vivado

#### 1. **Install Vivado Design Suite**

- **Download and Install**: Download the latest version of Vivado from the Xilinx website
and install it on your computer.
- **Licensing**: Obtain the necessary licenses for the features and devices you will be using.

#### 2. **Create a New Project**

- **Open Vivado**: Launch the Vivado Design Suite.
- **Create New Project**: Go to File > New Project, and follow the wizard.
- **Project Name and Location**: Specify the project name and directory.
- **Project Type**: Select RTL Project.
- **Add Sources**: Add existing HDL files or create new ones.
- **Add Constraints**: Add XDC constraint files if available (you can add them later as
well).
- **Select Device**: Choose the FPGA part or board you are targeting.

45
Experiment <TO BE FILLED BY STUDENT> Student ID <TO BE FILLED BY STUDENT>
Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

#### 3. **Design Entry**

- **Create HDL Code**: Write your logic circuit in VHDL or Verilog. Ensure your top
module matches the design's I/O requirements.
- **Add Source Files**: Add your HDL files to the project.
- Example (Verilog):
```verilog
module top_module (
input wire clk,
input wire reset,
input wire [3:0] a,
input wire [3:0] b,
output wire [7:0] result
);
// Your logic here
endmodule
```

#### 4. **Add Constraints**

- **XDC File**: Create or modify the constraints file (XDC). This file specifies pin
assignments and timing constraints.
- Example (XDC):
```tcl
set_property PACKAGE_PIN W5 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
```

#### 5. **Synthesize Design**

- **Run Synthesis**: Click on the "Run Synthesis" button in the Flow Navigator.
- **Check Reports**: Review the synthesis reports for any errors or warnings.

#### 6. **Implement Design**

- **Run Implementation**: Click on the "Run Implementation" button.
- **Check Timing**: Review the timing summary to ensure your design meets timing
constraints.

#### 7. **Generate Bitstream**

- **Run Bitstream Generation**: Click on the "Generate Bitstream" button.
- **Review**: Ensure that the bitstream generation completes successfully.

#### 8. **Program the FPGA**

- **Open Hardware Manager**: Open the Hardware Manager from Vivado.

46
Experiment <TO BE FILLED BY STUDENT> Student ID <TO BE FILLED BY STUDENT>
Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

- **Connect to FPGA**: Connect your FPGA development board to your computer via USB
and power it on.
- **Auto Connect**: Click on "Open Target" and select "Auto Connect".
- **Program Device**: Click on the "Program Device" button and select the generated
bitstream file (.bit).

#### 9. **Verify the Design**

- **Testing**: Verify the functionality of your design on the hardware. Use test inputs and
observe outputs using onboard LEDs, serial communication, or other peripherals.
- **Debugging**: If there are issues, use Vivado’s debugging tools such as ILA (Integrated
Logic Analyzer) and VIO (Virtual Input/Output) to diagnose and fix problems.

#### 10. **Iterate and Optimize**

- **Modify Design**: Based on testing and debugging, make necessary modifications to
your HDL code or constraints.
- **Re-synthesize**: Repeat the synthesis, implementation, and bitstream generation steps as
needed.

### Additional Tips

- **Simulate Before Synthesis**: Use the Vivado simulator to verify the logic functionality
before running synthesis.
- **Use IP Cores**: Take advantage of Xilinx IP cores for common functions like FIFOs,
DSP blocks, memory controllers, etc.
- **Documentation and Version Control**: Keep detailed documentation of your design and
use version control systems like Git to manage your source files.

By following these steps, you can successfully implement logic circuits on an FPGA using
the Xilinx Vivado Design Suite.

Prelab Questions

1. What is a FSM in FPGA design?

2. How do you optimize an FPGA design?

47
Experiment <TO BE FILLED BY STUDENT> Student ID <TO BE FILLED BY STUDENT>
Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

In-Lab:
• FPGA Implementation

48
Experiment <TO BE FILLED BY STUDENT> Student ID <TO BE FILLED BY STUDENT>
Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

• Analysis and Inferences:

Viva Questions

1. What is meant by elaborate design in vlsi semi custom flow.

2. Explain the hierarchical steps in cadence digital environment followed for simulation
using nclaunch.

References

- Cadence Virtuoso User Guide

- Digital Design and Computer Architecture by David Harris and Sarah Harris
- Verilog HDL by Samir Palnitkar
- Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey

49
Experiment <TO BE FILLED BY STUDENT> Student ID <TO BE FILLED BY STUDENT>
Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

Post-Lab:
5. T,iming violations in digital circuits

• Code and Waveform:

• Analysis and Inferences:

Evaluator Remark (if Any):

Marks Secured: _____out of 50

Signature of the Evaluator with Date

Evaluator MUST ask Viva-voce prior to signing and posting marks for each experiment

50
Experiment <TO BE FILLED BY STUDENT> Student ID <TO BE FILLED BY STUDENT>
Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

Exp no : 11

Undergo spice simulation of combinational circuits (minimum 10 transistors) using LTSpice and

undergo transient analysis

Aim

Undergo spice simulation of combinational circuits (minimum 10 transistors) using LTSpice and

undergo transient analysis

Prerequisites

Design using LTSpice

Software and Tools

LTSpice

Procedure

Prelab Questions

1. What is a the essence of spice modeling in VLSI

2. How do you optimize an FPGA design?

51
Experiment <TO BE FILLED BY STUDENT> Student ID <TO BE FILLED BY STUDENT>
Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

In-Lab:
• Spice Implementation

52
Experiment <TO BE FILLED BY STUDENT> Student ID <TO BE FILLED BY STUDENT>
Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

• Analysis and Inferences:

Viva Questions

1. What is meant by elaborate design in vlsi semi custom flow.

2. Explain the hierarchical steps in cadence digital environment followed for simulation
using nclaunch.

References

- Cadence Virtuoso User Guide

- Digital Design and Computer Architecture by David Harris and Sarah Harris
- Verilog HDL by Samir Palnitkar
- Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey

Post-Lab:
6. Spice implementation of large blocks.

53
Experiment <TO BE FILLED BY STUDENT> Student ID <TO BE FILLED BY STUDENT>
Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

• Code and Waveform:

• Analysis and Inferences:

Evaluator Remark (if Any):

Marks Secured: _____out of 50

Signature of the Evaluator with Date

Evaluator MUST ask Viva-voce prior to signing and posting marks for each experiment

54
Experiment <TO BE FILLED BY STUDENT> Student ID <TO BE FILLED BY STUDENT>
Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

Exp no : 12

Undergo spice simulation of sequential circuits (minimum 10 transistors) using LTSpice and undergo

transient analysis

Aim

Undergo spice simulation of sequential circuits (minimum 10 transistors) using LTSpice and undergo

transient analysis

Prerequisites

Design using LTSpice

Software and Tools

LTSpice

Procedure

Prelab Questions

1. What is a the essence of spice modeling in VLSI

2. How do you optimize an FPGA design?

55
Experiment <TO BE FILLED BY STUDENT> Student ID <TO BE FILLED BY STUDENT>
Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

In-Lab:
• Spice Implementation

56
Experiment <TO BE FILLED BY STUDENT> Student ID <TO BE FILLED BY STUDENT>
Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

• Analysis and Inferences:

Viva Questions

1. What is meant by elaborate design in vlsi semi custom flow.

2. Explain the hierarchical steps in cadence digital environment followed for simulation
using nclaunch.

References

- Cadence Virtuoso User Guide

- Digital Design and Computer Architecture by David Harris and Sarah Harris
- Verilog HDL by Samir Palnitkar
- Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey

Post-Lab:
7. Spice implementation of large blocks.

57
Experiment <TO BE FILLED BY STUDENT> Student ID <TO BE FILLED BY STUDENT>
Date <TO BE FILLED BY STUDENT> Student Name <TO BE FILLED BY STUDENT>

• Code and Waveform:

• Analysis and Inferences:

Evaluator Remark (if Any):

Marks Secured: _____out of 50

Signature of the Evaluator with Date

Evaluator MUST ask Viva-voce prior to signing and posting marks for each experiment

58