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Dsd Lab Report 12

This document details the implementation of a traffic light controller using a finite state machine (FSM) in a digital systems design lab. It includes objectives, lab tasks, Verilog code for the traffic light and clock divider, UCF file specifications, and a conclusion reflecting on the learning experience. The project aims to enhance understanding of FSMs and Verilog applications in practical scenarios.

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naveed2k03
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4 views5 pages

Dsd Lab Report 12

This document details the implementation of a traffic light controller using a finite state machine (FSM) in a digital systems design lab. It includes objectives, lab tasks, Verilog code for the traffic light and clock divider, UCF file specifications, and a conclusion reflecting on the learning experience. The project aims to enhance understanding of FSMs and Verilog applications in practical scenarios.

Uploaded by

naveed2k03
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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IMPLEMENT A TRAFFIC LIGHT

CONTROLLER USING
FSM
LAB # 12

Spring 2024

CSE-308L
Digital System Design Lab

Submitted by: Naveed Ahmad

Registration No.: 22PWCSE2165

Class Section: B

“I affirm that I have completed this work with integrity”

Student Signature:

Submitted to:

Engr. Shah Zada Fahim Jan


Sunday, June 2, 2024

Department of Computer Systems Engineering


University of Engineering and Technology, Peshawar
Implement A Traffic Light Controller Using FSM

Objectives:
➢ Continue the introduction to FSMs
➢ Mealy machine

Lab Tasks:
Task 1:
D < 3 sec
V=0 HG_FR V=1 HR_FY

H=001 F=100 H=100 F=010

D = 3 sec
D = 3 sec

HY_FR HR_FG

H=010 F=100 D = 10 sec H=100 F=001

D < 3sec D < 10 sec

Verilog Code:
module Traffic_lights(clk,rst,v,out_farm,out_highway);
input clk,rst,v;
output reg [2:0] out_farm, out_highway;
reg [1:0] PS,NS;
parameter [1:0] FR_HG = 0, FY_HR = 1, FG_HR = 2, FR_HY = 3;
parameter [2:0] red = 100, yellow = 010, green = 001;
wire out_clk;

clk_divider d1(clk,out_clk,rst);

always @(posedge out_clk)


if(rst==0)
begin
PS = FR_HG;
end
else
PS = NS;

always @(PS or v or rst)


case(PS)
FR_HG:
begin
NS = v?FY_HR: FR_HG;
out_highway = v?red:green;
out_farm = v?yellow:red;
end

FY_HR:
begin
NS = FG_HR;
out_highway = red;
out_farm = green;
end

FG_HR:
begin
NS = FR_HY;
out_highway = yellow;
out_farm = red;
end

FR_HY:
begin
NS = FR_HG;
out_highway = green;
out_farm = red;
end
endcase
endmodule

Clock Divider Code:


module clk_divider(input in_clk,output reg out_clk, input rst);
reg [100:0] count;
always @(posedge in_clk)
if(rst==0)
begin
out_clk = 0;
count = 0;
end
else
begin
count = count+1;
if(count==3*100000000)
begin
out_clk = ~out_clk;
count = 0;
end
end
endmodule
UCF File:

UCF file:
net "rst" LOC =K18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST
| PULLUP;
net "v" LOC =F17 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST |
PULLUP;
net "clk" LOC =V10 | IOSTANDARD = LVCMOS33 | period = 100MHz;

net "out_highway[0]" LOC = N16 | IOSTANDARD = LVCMOS33 | DRIVE = 8 |


SLEW = FAST;
net "out_highway[1]" LOC = U17 | IOSTANDARD = LVCMOS33 | DRIVE = 8 |
SLEW = FAST;
net "out_highway[2]" LOC = U18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 |
SLEW = FAST;
net "out_farm[0]" LOC = P15 | IOSTANDARD = LVCMOS33 | DRIVE = 8 |
SLEW = FAST;
net "out_farm[1]" LOC = P16 | IOSTANDARD = LVCMOS33 | DRIVE = 8 |
SLEW = FAST;
net "out_farm[2]" LOC = N15 | IOSTANDARD = LVCMOS33 | DRIVE = 8 |
SLEW = FAST;

Output:
References:
➢ To view my lab codes, please refer to the DCSE repository on my GitHub Account:
https://github.com/aimalexe/DCSE/tree/main/semester_6_(spring-
24)/digital_system_design_lab/lab_reports
➢ And so on…
➢

Conclusion:
In summary, our Digital Systems Design lab has been a success, enabling us to
achieve our objectives through hands-on tasks and theoretical exploration. This experience
has enhanced my understanding of fundamental concepts in Verilog and their practical
applications. I am excited to apply this knowledge in various contexts moving forward.

The End.

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