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TS3USB31
SCDS242E – JULY 2007 – REVISED AUGUST 2016

TS3USB31 1:1 SPST High-Speed USB 2.0 (480-Mbps) Bus Isolation Switch
With Single Enable
1 Features 3 Description
•
1 VCC Operation at 3 V and 4.3 V The TS3USB31 is a 1:1 SPST high-bandwidth switch
specially designed for the switching of high-speed
• 1.8-V Compatible Control-Pin Inputs USB 2.0 signals. This device comes in a small UQFN
• IOFF Supports Partial Power-Down Mode package for use in a handset or consumer
Operation applications, such as cell phones, digital cameras,
• ron = 10 Ω Maximum and notebooks with hubs. The wide bandwidth (750
MHz) of this switch allows signals to pass with
• Δron <0.35 Ω Typical
minimum edge and phase distortion. The switch is
• Cio(ON) = 6 pF Typical bidirectional and offers little or no attenuation of the
• Low Power Consumption (1 µA Maximum) high-speed signals at the outputs. It is designed for
• ESD Performance Tested Per JESD 22 low bit-to-bit skew and high channel-to-channel noise
isolation, and is compatible with various standards,
– 6000-V Human-Body Model such as high-speed USB 2.0 (480 Mbps).
(A114-B, Class II)
– 1000-V Charged-Device Model (C101) Device Information(1)
– 250-V Machine Model (A115-A) PART NUMBER PACKAGE BODY SIZE (NOM)

• Wide –3-dB Bandwidth = 1220 MHz Typical TS3USB31 UQFN (8) 1.50 mm × 1.50 mm

• Packaged in 8-Pin TQFN (1.5 mm × 1.5 mm) (1) For all available packages, see the orderable addendum at
the end of the data sheet.

2 Applications
Bus Isolation for USB 1.0, 1.1, and 2.0
Functional Block Diagram
HSD1+
D+

HSD1±
D±

OE Control

Copyright © 2016, Texas Instruments Incorporated

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 8.3 Feature Description................................................. 12
2 Applications ........................................................... 1 8.4 Device Functional Modes........................................ 12
3 Description ............................................................. 1 9 Application and Implementation ........................ 13
4 Revision History..................................................... 2 9.1 Application Information............................................ 13
9.2 Typical Application ................................................. 13
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 10 Power Supply Recommendations ..................... 15
6.1 Absolute Maximum Ratings ...................................... 4 11 Layout................................................................... 15
6.2 ESD Ratings.............................................................. 4 11.1 Layout Guidelines ................................................. 15
6.3 Recommended Operating Conditions....................... 4 11.2 Layout Example .................................................... 16
6.4 Thermal Information .................................................. 5 12 Device and Documentation Support ................. 17
6.5 Electrical Characteristics........................................... 5 12.1 Documentation Support ........................................ 17
6.6 Dynamic Electrical Characteristics............................ 5 12.2 Receiving Notification of Documentation Updates 17
6.7 Switching Characteristics .......................................... 6 12.3 Community Resource............................................ 17
6.8 Typical Characteristics .............................................. 6 12.4 Trademarks ........................................................... 17
7 Parameter Measurement Information .................. 8 12.5 Electrostatic Discharge Caution ............................ 17
12.6 Glossary ................................................................ 17
8 Detailed Description ............................................ 12
8.1 Overview ................................................................. 12 13 Mechanical, Packaging, and Orderable
8.2 Functional Block Diagram ....................................... 12
Information ........................................................... 17

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision D (July 2008) to Revision E Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1

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5 Pin Configuration and Functions

RSE Package
8-Pin UQFN
Top View

HSD–
N.C.

D–
7 6 5

VCC 8 4 GND

1 2 3

OE

HSD+

D+
RSE Package
8-Pin UQFN
Bottom View
HSD+
OE

D+

1 2 3

VCC 8 4 GND

7 6 5
HSD–

D–
N.C.

N.C. - No internal connection

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
Bus-switch enable, To isolate the D+/D- pins from the HSD+/HSD- pins set OE pin to valid
OE 1 I
high logic level, To connect D+/D- pins to HSD+/HSD- pins set OE pin to valid low logic level
D+ 3 I/O Data ports
D– 5 I/O Data ports
HSD+ 2 I/O Data ports
HSD– 6 I/O Data ports
N.C. 7 — No connect, This pin should be left floating or connect to ground
GND 4 — Ground
VCC 8 I/O Supply voltage

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage –0.5 7 V
(2) (3)
VIN Control input voltage –0.5 7 V
HSD+, HSD– –0.5 VCC + 0.3
(2) (3) (4)
VI/O Switch I/O voltage D+, D– when VCC > 0 –0.5 VCC + 0.3 V
D+, D– when VCC = 0 5.25
IIK Control input clamp current VIN < 0 –50 mA
II/OK I/O port clamp current VI/O < 0 –50 mA
(5)
II/O ON-state switch current ±64 mA
Continuous current through VCC or GND ±100 mA
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground, unless otherwise specified.
(3) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(4) VI and VO are used to denote specific conditions for VI/O.
(5) II and IO are used to denote specific conditions for II/O.

6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±6000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- V
±1000
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage 3 4.3 V
VCC = 3 V to 3.6 V 1.3
VIH High-level control input voltage V
VCC = 4.3 V 1.7
VCC = 3 V to 3.6 V 0.5
VIL Low-level control input voltage V
VCC = 4.3 V 0.7
VI/O Data input/output voltage 0 VCC V
TA Operating free-air temperature –40 85 °C

(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).

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6.4 Thermal Information

TS3USB31
THERMAL METRIC (1) RSE (UQFN) UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 115.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 38.4 °C/W
RθJB Junction-to-board thermal resistance 65.3 °C/W
ψJT Junction-to-top characterization parameter 5.4 °C/W
ψJB Junction-to-board characterization parameter 67.9 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) (1)
PARAMETER TEST CONDITIONS MIN TYP (2) MAX UNIT
Input Clamp
VIK VCC = 3 V, II = –18 mA –1.2 V
Voltage
IIN Control inputs VCC = 4.3 V or 0V, VIN = 0 to 4.3 V, ±1 µA
IOZ (3) VCC = 4.3 V, VO = 0 to 3.6 V, VI = 0, Switch OFF ±1 µA
IOFF D+ and D– VCC = 0 V, VO = 0 V to 4.3 V, VI = 0, VIN = VCC or GND ±2 µA
ICC VCC = 4.3 V, II/O = 0, Switch ON or OFF 1 µA
(4)
ΔICC Control inputs VCC = 4.3 V, VIN = 2.6 V 10 µA
Cin Control inputs VCC = 0 V, VIN = VCC or GND 1 pF
Off-state
Cio(OFF) Input/Output VCC = 3.3 V, VI/O = 3.3 V or 0, Switch OFF 2 pF
Capacitance
On-state
Cio(ON) Input/Output VCC = 3.3 V, VI/O = 3.3 V or 0, Switch ON 6 pF
Capacitance
On-State
ron (5) VCC = 3 V, VI = 0.4 V, IO = –8 mA 6 10 Ω
Resistance
Δron Channel Match VCC = 3 V, VI = 0.4 V, IO = –8 mA 0.35 Ω
On-State
ron(flat) Resistance VCC = 3 V, VI = 0 V or 1 V, IO = –8 mA 2 Ω
Flatness

(1) VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.
(2) All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
(3) For I/O ports, the parameter IOZ includes the input leakage current.
(4) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
(5) Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is
determined by the lower of the voltages of the two (A or B) terminals.

6.6 Dynamic Electrical Characteristics

over operating range, TA = –40°C to 85°C, VCC = 3.3 V ± 10%, GND = 0 V
PARAMETER TEST CONDITIONS TYP (1) UNIT
XTALK Crosstalk RL = 50 Ω, f = 240 MHz, See Figure 6 –53 dB
OIRR OFF isolation RL = 50 Ω, f = 240 MHz, See Figure 5 –30 dB
BW Bandwidth (–3 dB) RL = 50 Ω, CL = 5 pF, See Figure 7 1220 MHz

(1) For Max or Min conditions, use the appropriate value specified under Electrical Characteristics for the applicable device type.

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6.7 Switching Characteristics

over operating range, TA = –40°C to 85°C, VCC = 3.3 V ± 10%, GND = 0 V
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
RL = 50 Ω, CL = 5 pF,
tpd Propagation delay (2) (3) 0.25 ns
See Figure 8
RL = 50 Ω, CL = 5 pF,
tON Line enable time, OE to D, nD 30 ns
See Figure 4
RL = 50 Ω, CL = 5 pF,
tOFF Line disable time, OE to D, nD 25 ns
See Figure 4
RL = 50 Ω, CL = 5 pF,
tSK(O) Output skew between ports (2) 50 ps
See Figure 9
Skew between opposite transitions of the same output RL = 50 Ω, CL = 5 pF,
tSK(P) 20 ps
(tPHL – tPLH) (2) See Figure 9
RL = 50 Ω, CL = 5 pF,
tJ Total jitter (2) tR = tF = 500 ps at 480 Mbps 200 ps
(PRBS = 215 – 1)

(1) For Max or Min conditions, use the appropriate value specified under Electrical Characteristics for the applicable device type.
(2) Specified by design
(3) The bus switch contributes no propagational delay other than the RC delay of the on resistance of the switch and the load capacitance.
The time constant for the switch alone is of the order of 0.25 ns for 10-pF load. Since this time constant is much smaller than the rise/fall
times of typical driving signals, it adds very little propagational delay to the system. Propagational delay of the bus switch, when used in
a system, is determined by the driving circuit on the driving side of the switch and its interactions with the load on the driven side.

6.8 Typical Characteristics

0 0

-1 –10

–20
-2
–30
Attenuation (dB)

Attenuation (dB)

-3
–40
-4
–50
-5
–60
-6 –70

-7 –80

-8 –90
1.0E+06 1.0E+07 1.0E+08 1.0E+09 1.0E+10 100.0E+3 1.0E+6 10.0E+6 100.0E+6 1.0E+9 10.0E+9

Insertion Loss / Bandwidth Frequency (Hz)

Figure 1. Insertion Loss / Bandwidth Figure 2. OFF Isolation

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Typical Characteristics (continued)

0

–20

Attenuation (dB)
–40

–60

–80

–100

–120
100.0E+3 1.0E+6 10.0E+6 100.0E+6 1.0E+9 10.0E+9
Frequency (Hz)

Figure 3. Crosstalk

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7 Parameter Measurement Information

V CC

TEST RL CL V IN

1D or 2D V OUT1
t ON 50 Ÿ 5 pF V CC
D
V IN (B)
1D or 2D V OUT2 CL RL
t OFF 50 Ÿ 5 pF V CC

1.8 V
Logic Input
OE C L(B) RL 50% 50%
V 0
GND OE
t ON t OFF
VOE(A)
Switch V OH
90% 90%
Output
(V OUT1 or V OUT2) V OL

Figure 4. Turnon (tON) and Turnoff Time (tOFF)

V CC
Network Analyzer
Channel OFF: 1D to D
50 Ÿ
V OUT1 1D V(OE) = V(CC)
D V IN
Source
50 Ÿ 2D
Signal Network Analyzer Setup
Source Power = 0 dBm
V(OE) OE
(632-mV P-P at 50-Ÿ ORDG)
50 Ÿ + GND DC Bias = 350 mV

Figure 5. OFF Isolation (OIRR)

V CC
Netw o r k A n aly zer

Channel ON: 1D to D
50 Ÿ V OUT1 1D Channel OFF: 2D to D
V(OE)= V(CC)
V IN
Source
VOUT2 2D
S ig n al
Network Analyzer Setup
50 Ÿ
V(OE) OE
50 Ÿ Source Power= 0 dBm
+ (632-mV P-P at 50-Ÿ ORDG)
GND
DC Bias = 350 mV

Figure 6. Crosstalk (XTALK)

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Parameter Measurement Information (continued)

V CC
Network Analyzer

50 Ÿ V OUT1 1D Channel ON: 1D to D

D V IN V(OE) = GND
Source
2D
Signal
Network Analyzer Setup

50 Ÿ V(OE) OE Source Power = 0 dBm

(632-mV P-P at 50-Ÿ ORDG)
GND
DC Bias = 350 mV
GND

Figure 7. Bandwidth (BW)

800 mV
Input 50% 50%
400 mV

tPLH tPHL
VOH
Output 50% 50%
VOL

Figure 8. Propagation Delay

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Parameter Measurement Information (continued)

VOH

VOL

Pulse Skew tSK(P)

VOH

VOL

VOH

VOL

Output Skew tSK(P)

Figure 9. Skew Test

V CC

V OUT1 1D

D V IN
+ Channel ON
V OUT2 2D

ron = VIN ± VOUT or VOUT1

Ÿ
IIN
V(OE) I IN
OE V(OE) = VIH or VIL
+

GND

Figure 10. ON-State Resistance (ron)

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Parameter Measurement Information (continued)

V CC

V OUT1 1D

D V IN
+
V OUT2 2D +
OFF - State Leakage Current
Channel OFF
V(OE) = VIH or VIL
V(OE) OE
+

GND

Figure 11. OFF-State Leakage Current

V CC

V OUT1 1D
Capacitance
Meter VBIAS = VCC or GND
V OUT2 2D
V(OE) = VCC or GND
V IN D
VBIAS Capacitance is measured at 1D,
2D, D, and OE inputs during ON
V (OE) OE
and OFF conditions

GND

Figure 12. Capacitance

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8 Detailed Description

8.1 Overview
The TS3USB31 is a 1:1 SPST high-bandwidth switch specially designed for the switching of high-speed USB 2.0
signals. The switch is bidirectional and offers little or no attenuation of the high-speed signals. It is designed for
low bit-to-bit skew and high channel-to-channel noise isolation, and is compatible with various standards, such as
high-speed USB 2.0 (480 Mbps).

8.2 Functional Block Diagram

HSD1+
D+

HSD1±
D±

OE Control

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8.3 Feature Description

8.3.1 IOFF Supports Partial Power-Down Mode Operation

When VCC = 0 V, the signal path is placed in a high impedance state which isolates the bus. This allows signals
to be present on the D+/- and HSD+/- pins before the device is powered up without damaging the device.

8.4 Device Functional Modes

The TS3USB31 device has two modes that are digitally controlled by the OE pin. Setting the OE pin High
isolates the signal path by a high impedance state.

Table 1. Truth Table

OE FUNCTION
H Disconnect
L D+, D– = HSD+, HSD–

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TS3USB31 device is used to isolate a USB bus when it is not in use to prevent two different USB devices
from interfering with each other.

9.2 Typical Application

TS3USB31
VCC

USB
Base Band
Connector
Processor
or FS USB
Controller

HS USB
Controller

Copyright © 2016, Texas Instruments Incorporated

Figure 13. Application Diagram

9.2.1 Design Requirements

Design requirements of the USB 1.0, 1.1, and 2.0 standards should be followed. TI recommends that the digital
control pin OE be pulled up to VCC or down to ground to avoid undesired switch positions that could result from
the floating pin.

9.2.2 Detailed Design Procedure

The TS3USB31 can be properly operated without any external components. However, it is recommended that
unused pins be connected to ground through a 50-Ω resistor to prevent signal reflections back into the device.
The N.C pin should be left floating.

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Typical Application (continued)

9.2.3 Application Curves

0.5 0.5
0.4 0.4
0.3 0.3
Differential Signal (V)

Differential Signal (V)

0.2 0.2
0.1 0.1
0.0 0.0
–0.1 –0.1
–0.2 –0.2
–0.3 –0.3
–0.4 –0.4
–0.5 –0.5

0.0 0.2 0.4 0.5 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.0 0.2 0.4 0.5 0.8 1.0 1.2 1.4 1.6 1.8 2.0
–9 –9
Time (X 10 ) (s) Time (X 10 ) (s)

Figure 14. Eye Pattern: 480-Mbps USB Signal With No Figure 15. Eye Pattern: 480-Mbps USB Signal With Switch
Switch (Through Path) NO Path

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10 Power Supply Recommendations

Power to the device is supplied through the VCC pin. TI recommends placing a bypass capacitor as close as
possible to the supply pin VCC to help smooth out lower frequency noise to provide better load regulation across
the frequency spectrum.
This device doesn't require any power sequencing with respect to other devices in the system due to its power
off isolation feature which allows signals to be present on the D+/- and HSD+/- pins before the device is powered
up without damaging the device.

11 Layout

11.1 Layout Guidelines

Place supply bypass capacitors as close to VCC pin as possible and avoid placing the bypass caps near the D+
and D– traces.
The high-speed D+ and D– traces should always be of equal length and must be no more than 4 inches;
otherwise, the eye diagram performance may be degraded. A high-speed USB connection is made through a
shielded, twisted pair cable with a differential characteristic impedance. In layout, the impedance of D+ and D–
traces should match the cable characteristic differential impedance for optimal performance.
Route the high-speed USB signals using a minimum of vias and corners which will reduce signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the transmission line of the signal and increases the chance
of picking up interference from the other layers of the board. Be careful when designing test points on twisted
pair lines; through-hole pins are not recommended.
When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This
reduces reflections on the signal traces by minimizing impedance discontinuities.
Do not route USB traces under or near crystals, oscillators, clock signal generators, switching regulators,
mounting holes, magnetic devices, or IC’s that use or duplicate clock signals.
Avoid stubs on the high-speed USB signals because they cause signal reflections. If a stub is unavoidable, then
the stub should be less than 200 mm.
Route all high-speed USB signal traces over continuous planes (VCC or GND), with no interruptions.
Avoid crossing over anti-etch, commonly found with plane splits.
Due to high frequencies associated with the USB, a printed circuit board with at least four layers is
recommended: two signal layers separated by a ground layer and a power layer. The majority of signal traces
should run on a single layer, preferably top layer. Immediately next to this layer should be the GND plane, which
is solid with no cuts. Avoid running signal traces across a split in the ground or power plane. When running
across split planes is unavoidable, sufficient decoupling must be used. Minimizing the number of signal vias
reduces EMI by reducing inductance at high frequencies. For more information on layout guidelines, see High
Speed Layout Guidelines (SCAA082) and USB 2.0 Board Design and Layout Guidelines (SPRAAR7).

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11.2 Layout Example

= VIA to GND Plane

0603 Cap

To System Controller

Vcc
OE N.C

High Speed Bus High Speed Bus

HSD+ HSD-

High Speed Bus High Speed Bus

D+ D-

GND

Figure 16. Layout Recommendation

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following
• High Speed Layout Guidelines (SCAA082)
• USB 2.0 Board Design and Layout Guidelines (SPRAAR7)

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

12.3 Community Resource

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TS3USB31RSER ACTIVE UQFN RSE 8 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 L9

TS3USB31RSERG4 ACTIVE UQFN RSE 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 L9

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 13-Mar-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TS3USB31RSER UQFN RSE 8 3000 180.0 8.4 1.7 1.7 0.7 4.0 8.0 Q2
TS3USB31RSER UQFN RSE 8 3000 179.0 8.4 1.7 1.7 0.76 4.0 8.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 13-Mar-2022

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TS3USB31RSER UQFN RSE 8 3000 202.0 201.0 28.0
TS3USB31RSER UQFN RSE 8 3000 200.0 183.0 25.0

Pack Materials-Page 2
 PACKAGE OUTLINE
RSE0008A SCALE 7.000
UQFN - 0.6 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

1.55
B A
1.45

PIN 1 INDEX AREA

1.55
1.45

0.6 C
0.5

SEATING PLANE
0.05
0.00 0.05 C

0.35
2X
0.25 0.4
6X
0.1 C A B 0.3
(0.12)
0.05 C 0.45 TYP
2X
4 0.35

3
5

2X SYMM
1

0.25
2X
0.15
7
1 0.1 C A B
4X 0.5 0.05 C
8
0.3
SYMM 4X
0.2
0.1 C A B
PIN 1 ID
0.05 C
(45 X 0.1)

4220323/B 03/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

www.ti.com
 EXAMPLE BOARD LAYOUT
RSE0008A UQFN - 0.6 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

SYMM
(R0.05) TYP
8 2X (0.6)
6X (0.55)

1 7

4X (0.25)
SYMM
(1.3)
2X
4X (0.5) (0.2)

5
3

4
2X (0.3)
(1.35)

LAND PATTERN EXAMPLE

SCALE:30X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND
METAL SOLDER MASK
OPENING

SOLDER MASK
METAL
OPENING
UNDER
SOLDER MASK
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4220323/B 03/2018

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

www.ti.com
 EXAMPLE STENCIL DESIGN
RSE0008A UQFN - 0.6 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

SYMM

(R0.05) TYP 2X (0.6)

8

6X (0.55)

1 7

4X (0.25)
SYMM
(1.3)

4X (0.5) 2X (0.2)

5
3

4
2X
(0.3)

(1.35)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICKNESS
SCALE: 30X

4220323/B 03/2018

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
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