Department of Electrical & Electronic Engineering

Chittagong University of Engineering & Technology

EEE 476 VLSI Sessional
Experiment No.: 01
Draw the schematic of a 2-input NAND Gate, Create a Symbol and T
Perform Simulation

Learning Objectives:
 To login in to the Cadence Server shell and start the Cadence virtuoso software
 To create a working library
 To draw the schematic of a 2-input NAND gate in Cadence Virtuoso Schematic Editor
 To create a symbol view of the NAND gate from the schematic
 To simulate the NAND gate using MMSIM Spectre

1-1. Getting Started

1. Run Xming from the desktop. Then run putty.exe from your desktop. Under the Saved Sessions
dialog box click on VLSI and then click on Load. (confirm that Server IP address is
172.16.93.205, port is 22 and X forwarding is clicked) Next click on Open tab. Log in to
Cadence workstation using the username and password provided. Your user name will be groupx
and your password will be vlsi, where x is any number from 1 to 20.

2. After successful login, type $source .bashrc in a command window and type cd cds_work and
then press enter.

3. Type virtuoso & and virtuosos Command Interpreter Window (CIW) appears at the bottom of
the screen.

1-2. Creation of a Design Project and adding Library to the design

A unique directory should be created for each circuit design project. For you, the directory
cds_work is created by the administrator. So all your project works must be performed under this
directory.
First of all we will add the generalized 90 nm process design kit from cadence known as gpdk090
to our library path as follows.

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Adding the gpdk090 library to your library path

The Cadence® Library Path Editor helps you to define the libraries being used in your design. You
can set your cds.lib file or lib.defs file, or both, to point to the reference and design libraries you
want to use in your design. (However, in your case these directory may already has been added by
the administrator. You can verify this by checking the library paths)

1. In the CIW, execute Tools → Library Path Editor → Edit → Add Library. The add Library
form appears.
2. Add the “gpdk090” library from “/usr/local/cadence/local/gpdk090_v4.6/libs.0a22” and press ok

3. In the library path editor execute File →Save as. Make sure that both cds.lib and lib.defs are
selected.
Click OK the new paths will be saved and you will be able to use the above library.

4. Following the above procedure add the analogLib library from the following location
/usr/local/cadence/ic612/tools.lnx86/dfII/etc/cdslib/artist
5. Similarly add the library basic from the following location
/usr/local/cadence/ic612/tools.lnx86/dfII/etc/cdslib

Now we will create a working library to store our design and attach it to desired technology library.

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 6. In the CIW, execute File→ New→ Library
7. The new Library form appears. In the name field of the New Library type mylib.

8. In the field under the Directory Section, verify that the path to the library is set to
/home/groupx/cds_work
9. Select Attach to an existing technology library and click ok.
10. Attach Library to Technology Lib appears.

11. Select the gpdk90 technology library and click OK.

12. In the Library Manager window (Tools → Library Manager) verify that the mylib library
is listed.

1-3. Creating the schematic of a 2 input NAND Gate

Open a new schematic window in the mylib library and build the nand2 design. You will simulate
this design later on.
1. In the Command Interpreter Window (CIW) or Library manger execute File
→New→Cellview.
2. Set up the create new file form as follows –
Library Name – mylib
Cell Name – nand2
View name – schematic

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 Open with – Schematic L

3. Click Ok when done.

A blank schematic window for the nand2 design appears. In the schematic window execute
Create→Instance. Make sure that the View name field in the form is set to symbol. You
will update the Library Name, Cell Name, and the property values given in the table below as
you place each component. After you complete the Create instance form, move your cursor to
the schematic window and click left to place the component. The nand2 design contains the
following cells from the following library.
Library Name Cell Name Properties
gpdk090 nmos1v Total Width = 240n
gpdk090 pmos1v Total Width = 240n
If you place a component with wrong parameter values, use the
Edit→Properties→Objects command to change the parameters. Use the Edit→Move
command if you placed components in the wrong location.
4. After entering the components, click Cancel in the Create Instance form or press Esc with
your cursor in the schematic window.
5. Execute Create→ Pin. Enter the Pin Names Ain Bin Vdd Gnd, Select Direction to be input.
Place the pins and then follow the same process to create and place a pin name of out with
direction to be output.

6. Use Create →Wire to create the wire connections between pins and instances.

7. File →Check and save when your schematic looks like the following:

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1-4. Creating the Symbol View of a 2 input NAND Gate

1. In the nand2 schematic window execute Create → Cellview → From Cellview.

2. The Cellview From Cellview form appears. With the edit options function active, you can
control the appearance of the symbol to generate.

2. Verify that the From View Name field is set to schematic, and the To view Name field is set to
symbol, with the Tool/Data Type set as schematicSymbol.

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3. Click OK in the Cellview From Cellview form. The Symbol Generation Form appears. Change
the values such that Ain & Bin is at the left, Out is at the right, Vdd is at the top and Gnd at the
bottom:

4. Click OK and the default box-shaped symbol view is created as shown below:

5. Move your cursor over the symbol, until entire green rectangle is highlighted (selected). Click
left to select it.
6. Click the delete icon in the symbol window.
7. Execute Create → Shape → Line/Arc/Circle to draw the symbol shown in the final picture.
8. Move the labels to the desired location.
9. To save your edited symbol view to disk, click the Save icon in the symbol editor window. When
you save the final version, make sure it is bug-free. As in the schematic entry, check the CDS.log
window. It should display following message for the correctly designed symbol view:
“mylib nand2 symbol” saved.

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10. Now we can instantiate this symbol to build other circuits.

1-5. Simulation of a the 2 input NAND Gate

Open a new schematic window in the mylib library and build the nand2_sim design.
In the Command Interpreter Window (CIW) or Library manger execute File →New→ Cellview.
1. Set up the create new file form as follows –
Library Name – mylib
Cell Name – nand2_sim
View name – schematic
Open with – Schematic L
2. Click Ok when done.
A blank schematic window for the nand2_sim design appears. In the schematic window execute
Create →Instance. Make sure that the View name field in the form is set to symbol. You
will update the Library Name, Cell Name, and the property values given in the table below as
you place each component. After you complete the Create instance form, move your cursor to
the schematic window and click left to place the component. The nand_2 design contains the
following cells from the following library.
Library Name Cell Name Properties
mylib nand2
analogLib vdc DC voltage = 1.2V
analogLib gnd
analogLib vpulse Voltage1 = 0V, Voltage 2 = 1.2V, Delay time = 3ns, Rise time =
3ns, Fall time = 3ns, *Period = 40ns/50ns, *Pulse width =
20ns/25ns
analogLib cap Capacitance = 0.1pF

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4. After entering the components, click Cancel in the Create Instance form or press Esc with
your cursor in the schematic window.
5. Execute Create → Pin. Enter the Pin Names A & B, Select Direction to be input. Place the
pins and then follow the same process to create and place a pin name of O with direction to be
output.
6. Use Create →Wire to create the wire connections between pins and instances.
7. File → Check and save when your schematic looks like the following:

8. In the Schematic window execute Launch → ADE L. Analog Design Environment (ADE)
window will open.

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9. Set up the model libraries by executing Setup → Model Libraries. Select the following model
library: gpdk090_mos.scs. In this model library there are models to simulate various corners
like fast-fast (FF), fast-slow (FS), typical-typical(TT) etc. We will choose the section typical
from the section scroll bar and select the section 'TT_s1v'. These will enable us to use the TT
models of the 1.2 V MOS transistors.

10. Now choose the analysis to be done by Analysis → Choose. Select transient analysis to be
done. Provide stop time as 200ns.

11. Select the output to be plotted by executing Outputs → To be plotted → Select on

schematic in the ADE window. Select A, B and Ofrom the schematic to plot and save. The
ADE window should appear to be something like the following:

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12. We will create the netlistand run the simulation by executing the following in the ADE
environment Simulation → Netlist and Run. A netlist file will be created. The netlist is saved
in your simulation directory with name input.scs. The simulation will run and the output will
appear as shown below. You can toggle the visibility of the plots by clicking on the eye icons
under Vis column beside the Name column.

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13. Next we measure the falling propagation delay for input port B. To start it we go to Tools →
Calculator. The calculator window appears. Click on vt. Next select the pins B and O from the
schematic. Next click on the Enter symbol. You will see the expression related to the transient
voltages of the selected entities being stacked in the calculator.

14.Next select delay under the Special Functions tab in the Function Panel of the Calculator.
The parameters corresponding to the delay function appears on the screen.

15. Clear the Signal 1 and Signal 2 lines if there is any expression already present on those lines.
After that, Drag and drop VT(“/B”)from stack or simply type it on the Signal 1 line. Next do the
same for VT(“/O”). Enter the threshold value for both 1 and 2 to be 0.6. Choose Edge Number
1 and 2 to be 2. Choose rising for Edge Number 1 and falling for Edge Number 2. Click on
Apply and then go to Tools → Plot. This will calculate the falling propagation delay for input
port B.

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