ECE315 / ECE515

Lecture – 7 Date: 01.09.2016

• CG Amplifier
• Examples
• Biasing in MOS Amplifier Circuits
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Common Gate (CG) Amplifier
• CG Amplifier- Input is applied at
the Source and the output is
sensed at the Drain.
• The Gate terminal is used for
establishing appropriate bias
conditions for the transistor.
• Its characteristic can be studied through large-signal behavior as well.

• For large 𝑉𝑖𝑛 i.e. for 𝑉𝑖𝑛 > 𝑉𝑏 − 𝑉𝑇 : 𝑀1 is off and therefore: 𝑉𝑜𝑢𝑡 = 𝑉𝐷𝐷
1 W
I D  nCox Vb  Vin  VT 
2
• For lower 𝑉𝑖𝑛 :
2 L
1 W 2
Vout  VDD  I D RD  VDD   nCox Vb  Vin  VT   RD
2 L 
Vout  W  V  
• Then small signal gain is:    nCox Vb  Vin  VT   1  T   RD
Vin  L  Vin  
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Common Gate (CG) Amplifier (contd.)
Vout W
• Since, 𝜕𝑉𝑇 𝜕𝑉𝑖𝑛 = 𝜕𝑉𝑇 𝜕𝑉𝑆𝐵 = η:  nCox Vb  Vin  VT  1    RD
Vin L

Av  g m 1    RD

Non-inverting Amplifier Higher as compared to CS stage

KVL in loop-1: KVL in loop-2:

V
V1  out RS  Vin  0  V  V
RD Vout  ro  out  g mV1  g mbV1   out RS  Vin
 RD  RD
Vout ( g m  g mb )ro  1
 Av  RD
Vin ro  ( g m  g mb )ro RS  RS  RD
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CG Amplifier (contd.) Non-inverting with slightly higher
value as compared to the CS
Vout ( g m  g mb )ro  1 stage → body effect is useful in
 Av  RD
Vin ro  ( g m  g mb )ro RS  RS  RD this scenario

• If the resistor RD is replaced Vout RD → ∞ for an ideal

by a current source then:  Av  ( gm  g mb )ro  1 current source
Vin

• Let us look at small-signal model – without channel length modulation and biased
with a constant current source

Vout
KVL in loop-1: KCL at this  Av   ( gm  gmb ) RD  gm (1   ) RD
Vin
v1  vin  0 node
V
( g m  g mb )V1  out  0
RD
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CG Amplifier (contd.)

• Input Impedance:
KVL in loop-1: KVL in loop-2:
V1  VX
RD I X  ro  I X  ( gm  gmb )VX   VX

VX RD  ro RD 1
Rin    
I X 1  ( gm  g mb )ro ( g m  g mb )ro ( g m  g mb )
VX ro
• Case-I: RD  0 Rin  
I X 1  ( g m  g mb )ro

• Case-II: RD is an ideal current source ie, RD →∞ Rin  

It is apparent that the input impedance of common-gate stage is low

only if the load impedance connected to the drain is low
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CG Amplifier (contd.)

• Output Impedance:
Rout  1  ( gm  gmb )ro  RS  ro  RD

Example – 1
• Derive the small-signal voltage
gain expression for this amplifier.
Consider the cases when
channel length modulation are
absent and present.
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Example – 1 (contd.)
• Case-I: λ = 0 both for M1 and M2 → In such a case M2 presents a
degenerating impedance of 1/gm2 to a single stage CS amplifier as shown
below.

1 Vout
gm2   g m1V1
RD
1  g 
Vin  V1  g m1V1.  V1 1  m1 
gm2  gm2 

Simplification gives: Vout   g m1V1RD  Av  

RD
1 1
g m 2 .Vin 
 Vout   g m1RD . g m1 g m 2
g m 2  g m1
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Example – 1 (contd.)
• Case-II: λ = 0 for M1 and λ ≠ 0 for M2 → In such a case M2 presents a
degenerating impedance of (1/gm2║ro2) as shown below.

1
ro 2 Vout
1
gm2   g m1V1
ro 2 RD
gm2  1    1 
Vin  V1  g m1V1. ro 2   V1 1  g m1  ro 2  
 gm2    gm2 

RD
 Av  
Simplification gives: 1  1 
 ro 2 
g m1  g m 2 
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Example – 1 (contd.)
• Case-III: λ = 0 for M2 and λ ≠ 0 for M1 → In such a case the small
signal model looks like:

g m1V1 ro1

1
gm2
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Example – 2
• Derive expression for the small-signal voltage gain of the following circuit.
(Assume: λ ≠ 0 for both M1 and M2. Neglect body effect)

Gate and Source are fixed.

Therefore this NMOS
works as a constant
current source with an
impedance ro2 across its
drain and source

g m1 (Vin  Vout )(ro1 ro 2 )  Vout

KVL in loop-1
KVL in Vout (ro1 ro 2 )
 Av  
Vin  V1  Vout loop-2 Vin  1 
g  ( r ro2 
)
g m1V1 (ro1 ro 2 )  Vout  m1
o1

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Example – 3
• What is Rout in the following circuit. (Assume: λ ≠ 0 for both M1 and M2
and both are in saturation.)

Gate and Source are fixed. Therefore this NFET

works as a constant current source with an
impedance ro2 across its drain and source

VX
  ro 2  ro1  ro1 ( g m1ro 2  g mb1ro 2 )  Rout
IX
KVL in loop-1 KVL in loop-2
V1   I X ro 2
VX  I X ro 2  ( I X  g m1V1  g mb1V1 )ro1
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Biasing using Single Power Supply
• The general form of a • We typically attempt to satisfy three main
single-supply MOSFET bias design goals:
amplifier biasing circuit is:
1) Maximize Gain
Typically, the small-signal voltage gain
of a MOSFET amplifier will be
Av  gm
proportional to transconductance 𝑔𝑚 .
Thus, to maximize the amplifier voltage gain, we must
maximize the MOSFET transconductance.

Q: What does this have to do with D.C. biasing?

A:

Recall that the transconductance g  2 K V  V
depends on the DC excess gate voltage: m GS T 

• Another way to consider transconductance is to express it in

terms of DC drain current 𝐼𝐷 .
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Biasing using Single Power Supply (contd.)
• Recall this DC current is ID
ID  K VGS  VT  VGS  VT  
2
related to the DC excess gate 
K
voltage (in saturation!) as:
ID
• And so transconductance can be gm  2 K VGS  VT   2 K  2 KID
alternatively expressed as: K

• Therefore, the amplifier voltage gain is typically

Av  ID
proportional to the square-root of the DC drain current:

To maximize 𝐴𝑣 , maximize 𝐼𝐷
2) Maximize Voltage Swing
Recall that if the DC drain voltage 𝑉𝐷 is biased
too close to 𝑉𝐷𝐷 , then even a small small-signal vD(t )  VD  vd (t )  VDD
drain voltage 𝑣𝑑 (𝑡) can result in a total drain
voltage that is too large, i.e.:
In other words, the MOSFET enters cutoff, and the result is a distorted signal!
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Biasing using Single Power Supply (contd.)
• To avoid this (to allow 𝑣𝑑 (𝑡) to be as large as possible without MOSFET entering
cutoff), we need to bias our MOSFET such that the DC drain voltage 𝑉𝐷 is as small
as possible.
• Note that the drain voltage is: VD  VDD  RD ID
• Therefore 𝑉𝐷 is minimized by designing the bias circuit such that the DC drain
current 𝐼𝐷 is as large as possible.
• However, we must also consider the signal distortion that occurs when the
MOSFET enters triode. This of course is avoided if the total drain-to-source
voltage remains greater than the excess gate voltage, i.e.:
vDS (t )  VDS  vds (t )  VGS  VT 
• Thus, to avoid the MOSFET triode mode—and the resulting signal distortion—we
need to bias our MOSFET such that the DC voltage is as large as possible.
To minimize signal distortion, maximize 𝑉𝐷𝑆
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Biasing using Single Power Supply (contd.)
3) Minimize Sensitivity to changes in 𝑲, 𝑽𝑻
• We find that MOSFETs are sensitive to temperature—specifically, the value of
𝐾 is a function of temperature.
• Likewise, the values of 𝐾 and 𝑉𝑇 are not particularly constant with regard to the
manufacturing process.
• Both of these facts lead to the requirement that our bias design be insensitive to
the values of 𝐾 and 𝑉𝑇 . Specifically, we want to design the bias network such
that the DC bias current does not change values when 𝐾 and/or 𝑉𝑇 does.
• Mathematically, we can express this d ID d ID
and
requirement as minimizing the value: dK dVT
• These derivatives can be minimized by maximizing the value of source resistor 𝑹𝑺 .

• So, let’s recap what we have 1. Make 𝐼𝐷 as large as possible.

learned about designing our 2. Make 𝑉𝐷𝑆 as large as possible.
bias network: 3. Make 𝑅𝑆 as large as possible.
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Biasing using Single Power Supply (contd.)

VDD  IDRD  VDS  IDRS  0

or
IDRD  VDS  IDRS  VDD

Maximize Av by But the total of

maximizing the three terms
this term. must equal this!

Minimize distortion Minimize sensitivity

by maximizing this by maximizing this
term. term.
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Example – 1

• If the MOSFET has device values 𝐾 = 1.0 𝑚𝐴 𝑉 2

and 𝑉𝑇 = 1.0𝑉, determine the resistor values to bias
this MOSFET with a DC drain current of 𝐼𝐷 = 4.0𝑚𝐴.
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The MOSFET Current Mirror
• Consider the following • Note 𝑉𝐷 = 𝑉𝐺 , therefore: VDS  VGS
MOSFET circuit:
• and thus: VDS  VGS  VT

• The MOSFET is in saturation if 𝑽𝑮 > 𝑽𝑻 .

• We know that for a MOSFET in
VDS  VGS
saturation, the drain current is:

Say we want this current 𝐼𝐷 to be a specific value—call it 𝐼𝑟𝑒𝑓 .

• Since 𝑉𝑆 = 0, we find that from the above Iref

equation, the drain voltage must be: VD   VT
K
• And thus the resistor
• Likewise, from VDD  VD value to achieve the VDD  VD
KVL we find Iref  desired drain current R 
that: R Iref
𝐼𝑟𝑒𝑓 is:
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The MOSFET Current Mirror (contd.)
Q: Why are we doing this?
A: Say we now add another component
to the circuit, with a second MOSFET that
is identical to the first :

Q: So what is current 𝑰𝑳 ?

A: Note that the gate voltage of each MOSFET is the same (i.e., 𝑉𝐺𝑆1 = 𝑉𝐺𝑆2 ),
and if the MOSFETS are the same (i.e., 𝐾1 = 𝐾2 , 𝑉𝑇1 = 𝑉𝑇2 ), and if the second
MOSFET is likewise in saturation.
IL  K2 VGS 2  VT 2 
2

• The drain current 𝑰𝑳 is:

 K1 VGS 1  VT 1   Iref
2

Therefore, the drain current of the second MOSFET is

equal to the current of the first! Iref  IL
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The MOSFET Current Mirror (contd.)
Q: Wait a minute! You mean to say that the current through the resistor RL is
independent of the value of resistor RL?
A: Absolutely! As long as the second MOSFET is in saturation, the current through
RL is equal to Iref—period.

• The current through RL is

independent of the value of
RL (provided that the MOSFET
remains in saturation). Think
about what this means—this
device is a current source !

• Remember, the second MOSFET

must be in saturation for the current V
DS 2  VGS 2 VT 2
through RL to be a constant value
𝐼𝑟𝑒𝑓 . As a result, we find that: • For this example: VD 2  VG 2 VT 2
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The MOSFET Current Mirror (contd.)
• Since 𝑉𝐷2 = 𝑉𝐷𝐷 − 𝑅𝐿 𝐼𝑟𝑒𝑓 , we find that the
VDD  RL Iref  VG2  VT 2  VG1  VT 1
MOSFET will be in saturation if:
• Alternatively, we find the limitation on VDD  VG1  VT 1
RL 
the load resistor RL: Iref

• We know that: VG 1  VDD  R Iref

• Thus we can alternatively VT 1

RL  R 
write the above equation as: Iref

• If the load resistor becomes larger than 𝑹 + 𝑽𝑻𝟏 𝑰𝒓𝒆𝒇 , the voltage 𝑽𝑫𝑺𝟐 will drop
below the excess gate voltage 𝑽𝑮𝑺𝟐 − 𝑽𝑻𝟐 , and thus the second MOSFET will
enter the triode region. As a result, the drain current will not equal 𝑰𝒓𝒆𝒇 —the
current source will stop working!
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The MOSFET Current Mirror (contd.)
Although the circuit is sometimes referred to as a current sink, understand that
the circuit is clearly a way of designing a current source.

• We can also use

PMOS devices to
construct a
current mirror!
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MOSFET Biasing using Current Mirror
• We can bias a MOSFET It is evident that the DC drain current ID, is equal to
amplifier using a current the current source I, regardless of the MOSFET
source as: values K or VT!

Thus, this bias design maximizes drain current stability!

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MOSFET Biasing using Current Mirror (contd.)
• We now know how to implement this • Since 𝐼𝐷 = 𝐼, it is evident that
bias design with MOSFETs—we use the 𝑉𝐺𝑆 must be equal to:
current mirror to construct the current
source! I
VGS  VT
K

• Since the DC gate voltage is:

 R2 
VG  VDD  
R
 1  R2 

• Therefore:
VS  VG VGS
 R2   I 
 VDD     VT 
 R1  R2   K 
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MOSFET Biasing using Current Mirror (contd.)
• Since we are biasing with a current source, we do not need to worry about drain
current stability—the current source will determine the DC drain current for all
conditions (i.e., 𝐼𝐷 = 𝐼).
• We might conclude, therefore, that we should make DC source voltage VS as
small as possible. After all, this would allow us to maximize the output voltage
swing (i.e., maximize 𝐼𝐷 𝑅𝐷 and 𝑉𝐷𝑆 ).
• Note however, that the source voltage 𝑉𝑆 of the MOSFET is numerically equal to
the drain voltage 𝑉𝐷2 (and thus 𝑉𝐷𝑆2 ) of the second MOSFET of the current
mirror.
Q: So what?!
A: The voltage must be greater than: VGS 2 VT 2 VGS 1 VT 1
 VDD  Iref R  VT 1
in order for the second MOSFET to remain in saturation.
There is a minimum voltage across the current source in order
for the current source to properly operate!
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MOSFET Biasing using Current Mirror (contd.)
• Thus, to maximize output
VS VGS 1 VT 1
swing, we might wish to set:
(although to be practical, we should make 𝑉𝑆 slightly
greater than this to allow for some design margin).
Q: How do we “set” the DC source voltage 𝑉𝑆 ??
A: By setting the DC gate voltage 𝑉𝐺 !!
• Recall that the DC voltage I
𝑉𝐺𝑆 is determined by the DC VGS  VT
current source value I: K

• and the DC gate voltage is determined by the two  R2 

VG  VDD  
resistors 𝑅1 and 𝑅2 : R
 1  R2 
VG VGS VS
• Thus, we should select these resistors
 I 
such that:  VT   VGS 1 VT 1 
 K 
 
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MOSFET Biasing using Current Mirror (contd.)
Q: So what should the value of resistor R D be?
A: Recall that we should set the DC drain voltage VD :
a) much less than VDD to avoid cutoff.
b) much greater than 𝑉𝐺 − 𝑉𝑇 to avoid triode.
• Thus, we compromise by setting the DC drain VDD  VG VT 
VD 
voltage to a point halfway in between! 2
• To achieve this, we must select the VDD VD VDD  VG VT 
RD  
drain resistor 𝑅𝐷 so that: ID ID
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Example – 2
Let’s determine the proper resistor values to DC bias this MOSFET. The current
source is 5.0 mA and has a minimum voltage of 2.0 Volts in order to operate
properly
• Since 𝐼 = 𝐼𝐷 = 5 𝑚𝐴 , we I
VGS   VT
know that the value of 𝑉𝐺𝑆 K
should be: 5.0
  1 .0
0.2
 6.0 V

• Assuming that we want the DC

VG  VGS  VS
source voltage to be the
minimum value of 𝑉𝑆 = 2.0𝑉,  6.0  2.0
we need for the DC gate  8.0 V
voltage to be:
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Example – 2 (contd.)
 R2 
V
• Thus, we need to select resistors 𝑅1 and 𝑅2 so that: G  8. 0  VDD  
R
 1  R2 

• or in other words, we want:  R2  8.0

 
R
 1  R2  15.0

• Since we can make 𝑅1 and 𝑅2 large, let’s

R1  R2  300K
assume that we want:

So that 𝑅1 = 140 𝑘Ω and 𝑅2 = 160 𝑘Ω .

VDD  VG VT 

• Finally, we want the DC drain voltage to be: VD 
2
15.0   8.0  1.0 
V V 
RD  DD D 2
• So that the resistor is: ID  11.0 V
15.0  11.0

5.0
 0.8 K
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Example – 2 (contd.)