UNIT 5:

Low – Power
UNIT-5: CMOS Logic
INTRODUCTION TO TESTING
Circuits
Design for Testability: Introduction
• The task of determining whether fabricated chips are fully
functional is highly complex and can be very time-
consuming.

• However, when faulty chips pass an improperly designed test,

they can cause system failures and enormous difficulty in system
debugging.

• It is known that the debugging cost increases by about tenfold from

chip level to board level, and also from board level to system level.

• Thus, it is of great importance to detect faults as early as possible.

As the number of transistors integrated into a single chip
increases, the task of chip testing to ensure correct functionality
becomes increasingly more difficult.
 Introduction (Contd.)
• In a production environment, many chips must be
tested within a short time for timely delivery to
customers.

• To overcome such difficult issues, design for testability

has become ever more critical.

• In this chapter, we discuss types of faults, the

corresponding fault models, design of testable circuits,
and self-testing circuits.

• The testability will be defined in terms of observability

and controllability, which are also commonly used in
control and system theory.
 Fault Types and Models
Examples of physical defects include:

* Defects in silicon substrate

* Photolithographic defects
* Mask contamination and scratches
* Process variations and abnormalities
* Oxide defects

The physical defects can cause electrical faults and

logical faults.
The electrical faults include:

• Shorts (bridging faults)

• Opens Transistor stuck-on, stuck-open
• Resistive shorts and opens
• Excessive change in threshold voltage
• Excessive steady-state currents

The electrical faults in turn can be translated into

logical faults.
The logical faults include:

• Logical stuck-at-0 or stuck-at-I

• Slower transition (delay fault)
• AND-bridging, OR-bridging
• The relationships between physical defects, electrical
faults, and logical faults can be explained using a
simple NOR2 gate as shown in Fig.

• A metallic blob (physical defect) between the common

drain terminal in the n-diffusion region and the ground
bus line shown in Fig.(a) can be modeled as a resistive
short between the output node Z and the ground as shown
in Fig.(b),

• And also by a stuck-at-0 (s-a-0) fault of output Z when

the resistance is low or a pull-up delay fault when the
resistance is high, as shown in Fig.(c).
Fig. (a) Physical defect in NOR2 fabrication, (b) its electrical fault model; and (c) its
logical fault models.
• The single stuck-at fault models are used frequently, although
the DUT can have defects that do not map to a single stuck-at
fault. Some of the reasons are:

• Complexity of test generation is greatly reduced.

• Single stuck-at fault is independent of technology, design style.

• Single stuck-at tests cover a large percentage of multiple stuck-

at faults.

• Single stuck-at tests cover a large percentage of unmodeled

physical defects.
Some process-related defects in a CMOS circuit consisting of NOR2,
NAND2, and inverter gates.
 UNIT 5:
Low – Power CMOS Logic
Circuits
UNIT-5: INTRODUCTION TO TESTING
 Controllability and Observability
• The controllability of a circuit is a measure of
the ease (or difficulty) with which the controller
(test engineer) can establish a specific signal
value at each node by setting values at the
circuit input terminals.

• The observability is a measure of the ease (or

difficulty) with which one can determine the
signal value at any logic node in the circuit by
controlling its primary input and observing
the primary output.
• The term primary refers to the I/O boundary of the
circuit under test.

• The degree of controllability and observability and, thus,

the degree of testability of a circuit, can be measured
with respect to whether test vectors are generated
deterministically or randomly.

• For example, if a logic node can be set to either logic 1 or

0 only through a very long sequence of random test
vectors, the node is said to have a very low random
controllability since the probability of generating such a
vector in random test generation is very low.
• There exist time constraints in practice, and in such cases the circuit
may not be considered testable.

• There are deterministic procedures for test generation for

combinational circuits, such as the D-algorithm which uses a recursive
search procedure advancing one gate at a time and backtracking, if
necessary, until all the faults are detected.

• The D-algorithm requires a large amount of computer time. To

overcome such shortcomings, many improved algorithms such as Path-
Oriented DEcision Making (PODEM) and FAN-out-oriented test
generation (FAN) have been introduced, Sequential circuit test
generation is several orders of magnitude more difficult than these
algorithms.

• To ease the task of ATG, design-for-test (DFT) techniques are routinely

employed.
Fig. A simple circuit consisting of four gates with four primary inputs and one
primary output.
• To detect any defect on line 8, the primary inputs A and B must be set
to logic 1.
• However, such a setting forces line 7 to logic 1. Thus, any stuck-at- (s-a-
1) fault on line 7 cannot be tested at the primary output, although in the
absence of such a fault, the logic value on line 7 can be fully controllable
through primary inputs B, C, and D.

• Therefore, this circuit is not fully testable. The main cause of this
difficulty in this circuit is the fact that input B fans out to lines 5 and 6,
and then after the OR3 gate, both line signals are combined in the AND3
gate.

• Such a fanout is called reconvergent fanout.

• Reconvergent fanouts make the testing of the circuit much more difficult.
• If a large number of input vectors are required to set
a particular node value to 1 or 0 (fault excitation) and
to propagate an error at the node to an output (fault
effect propagation), then the testability is low.

• The circuits with poor controllability include those

with feedbacks, decoders, and clock generators.

• The circuits with poor observability include

sequential circuits with long feedback loops and
circuits with reconvergent fanouts, redundant nodes,
and embedded memories such as RAM, ROM, and
PLA.
 UNIT 5:
Low – Power CMOS Logic
Circuits
UNIT-5: INTRODUCTION TO TESTING
 Ad Hoc Testable Design Techniques
• One way to increase the testability is to make
nodes more accessible at some cost by
physically inserting more access circuits to the
original design.
Ad hoc testable design techniques:
• Partition-and-Mux Technique
• Initialize Sequential Circuit
• Disable Internal Oscillators and Clocks
• Avoid Asynchronous Logic and Redundant Logic
• Avoid Delay-Dependent Logic
 Partition-and-Mux Technique
• Since the sequence of many serial gates, functional blocks, or large circuits
are difficult to test, such circuits can be partitioned.

• Multiplexors (muxes) can be inserted such that some of the primary inputs can
be fed to partitioned parts through multiplexers with accessible control signals.

• With this design technique, the number of accessible nodes can be increased and
the number of test patterns can be reduced.

• A case in point would be the 32-bit counter. Dividing this counter into two 16-
bit parts would reduce the testing time in principle by a factor of 215.

• However, circuit partitioning and addition of multiplexers may increase the

chip area and circuit delay.

• This practice is not unique and is similar to the divide-and-conquer approach to

large, complex problems.
 Initialize Sequential Circuit
• When the sequential circuit is powered up, its initial
state can be a random, unknown state.

• In this case, it is not possible to start the test

sequence correctly.

• The state of a sequential circuit can be brought to a

known state through initialization.

• In many designs, the initialization can be easily done by

connecting asynchronous preset or clear-input signals
from primary or controllable inputs to flip-flops or latches.
Disable Internal Oscillators and Clocks
• To avoid synchronization problems during
testing, internal oscillators and clocks
should be disabled.
• For example, rather than connecting the
circuit directly to the on-chip oscillator,
the clock signal can be ORed with a
disabling signal followed by an insertion of
a testing signal as shown in Fig.
 Avoid Asynchronous Logic and
Redundant Logic
• The redundant node cannot be observed since the
primary output value cannot be made dependent on the value of
the redundant node.

• Hence, certain faults on the redundant node cannot be tested or

detected.

• Figure shows that the bottom NAND2 gate is redundant and

the stuck-at- fault on its output line cannot be detected.

• If a fault is undetectable, the associated line or gate can be

removed without changing the logic function.
 Avoid Delay-Dependent Logic
• Chains of inverters can be used to design in delay
times and use AND operation of their outputs along
with inputs to generate pulses.
• Most automatic test pattern generation (ATPG)
programs do not include logic delays to minimize
the complexity of the program.
• As a result, such delay-dependent logic is viewed as
redundant combinational logic, and the output of the
reconvergent gate is always set to logic 0, which is
not correct.
• Thus, the use of delay-dependent logic should
be avoided in design for testability.
 UNIT 5:
Low – Power CMOS Logic
Circuits
Scan-Based Techniques
• Step 1: Set the mode to test and, let latches accept data
from scan-in input,
• Step 2: Verify the scan path by shifting in and out the
test data.
• Step 3: Scan in (shift in) the desired state vector into the
shift register.
• Step 4: Apply the test pattern to the prim ary input pins. I : ;
• Step 5: Set the mode to normal and observe the primary
outputs of the circuit after sufficient time for propagation.
• Step 6: Assert the circuit clock, for one machine cycle
to capture the outputs of the combinational logic into
the registers.
• Step 7: Return to test mode; scan out the contents of the
registers, and at the same time scan in the next pattern.
• Step 8: Repeat steps 3-7 until all test patterns are applied.
• The storage cells in scan design can be implemented using edge-
triggered D flipflops, master-slave flip-flops, or level-sensitive
latches controlled by complementary clock signals to ensure
race- free operation.

• Figure shows a scan-based design of an edge-triggered D flip-flop.

• In large high-speed circuits, optimizing a single clock signal for

skews, etc., both for normal operation and for shift operation,
is difficult.

• To overcome this difficulty, two separate clocks, one for normal

operation and one for shift operation, are used.
Built-In Self Test (BIST) Techniques
• In built-in self test (BIST) design, parts of
the circuit are used to test the circuit itself.
• Online BIST is used to perform the test under
normal operation, whereas off-line BIST is used
to perform the test off-line.

The essential circuit modules required for BIST

include:
• Pseudo random pattern generator (PRPG)
• Output response analyzer (ORA)
Pseudo Random Pattern Generator
• To test the circuit, test patterns first have to
be generated either by using a pseudo
random pattern generator, a weighted test
generator, an adaptive test generator, or
other means.

• A pseudo random test generator circuit

can use an LFSR
A procedure for BIST
A pseudo-random sequence generator using
LFSRA pseudo-random sequence generator
using LFSR
 Linear Feedback Shift Register as an
ORA
• To reduce the chip area penalty, data compression schemes
are used to compare the compacted test responses instead of
the entire raw test data.

• One of the popular data compression schemes is the

signature analysis, which is based on the concept of cyclic
redundancy checking.

• It uses polynomial division, which divides the polynomial

representation of the test output data by a characteristic
polynomial and then finds the remainder as the
signature.

• The signature is then compared with the expected signature to

determine whether the device under test is faulty.
 Output Response Analyzer
• A simple alternative method is to compare the
outputs of two identical circuits for the same input,
with one of them regarded as reference.

• In addition to the above circuits for built-in self test,

self-checking design techniques can be used to
detect faults autonomously during on-line operation.

• Usually a checker circuit is inserted such that the

checker generates and sends out a signal when on-
line faults occur.
 Built-In Logic Block Observer
• The built-in logic block observer (BILBO)
register is a form of ORA which can be used
in each cluster of partitioned registers.
• A basic BILBO circuit is which allows
four different modes controlled by C0
and Cl signals.
3-bit built-in logic observer (BILBO)
example