2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), 16-19 October 2016, Abu Dhabi,

UAE

Low Power Multi Threshold 7T SRAM Cell

Divyesh Sachan, Harish Peta, Kamaldeep Singh Malik, Manish Goswami*
Department of Electronics and Communication Engineering
Indian Institute of Information Technology
Allahabad, India
*email: [email protected]

Abstract— Technologies like Internet of Things (IoT) are SRAM [3] cell. The simulation result shows the decrease in
bringing new challenges to IC design, where power dissipation is standby power dissipation and increased stability in read and
desired to be less for portable devices. Further scaling of devices write operation using multi thresholding technique.
for portability requires reliable memories which can be operated
at lower voltages. In this paper, a modified 7T SRAM cell has
been proposed with high static noise margin. The proposed 7T II. PROPOSED DESIGN
RAM has been compared with conventional 6T SRAM and LP7T Fig. 1 shows the proposed 7T SRAM bit cell considering
SRAM in terms of static noise margins and power. The SNM metrics like size, power and SNM. A cell ratio (CR) of 1 (CR
results show an increase of 48% and 78% over the standard 6T = WNM1 / WNM2 = WNM0 / WNM3) is considered as a
for writing 0 and 1 respectively, 122% increase in RSNM when design metric to show that it provides a very good stability
compared to standard 6T SRAM bit cell and slightly better even without increasing the area [1]. The proposed design has
results than LP 7T bit cell for RSNM and Hold SNM when a latch, consisting of back-to-back connected inverters (NM0-
simulated in Cadence virtuoso using 65nm CMOS technology. PM0 and NM1-PM1), a tail transistor NM5 to reduce the static
The proposed design uses 50% and 16.5% less power compared power dissipation during read and idle states using stacking
to standard 6T SRAM for dynamic write and read respectively.
effect, two NMOS access transistors NM2 and NM3 for write
The Monte Carlo simulation on process and mismatch
parameters shows a very small deviation.
operation and a high threshold voltage NMOS transistor NM4.
The tail transistor is not a part of the bit cell as is connected
Keywords— 7T SRAM, low power, noise margin, SNM, random using power gating to a whole row of SRAM bit cells. The
access memory, bit cell length of all the transistor is 65nm.

I. INTRODUCTION
An exponential increase in demand for portable devices
resulted in the aggressive scaling down of devices. In
nanoscale technology, smaller device dimensions are prone to
manufacturing variations which can lower read/write stability.
Presently, semiconductor companies are focusing on
manufacturing more reliable memories, with low operating
voltage and low power consumption. Memory is broadly
divided into two types- dynamic random access memory
(DRAM) and static random access memory (SRAM). An
efficient and reliable SRAM is designed as cache memory to
achieve high speed by providing a direct interface with the
central processing unit (CPU). To make CPU faster, a cache is
built along with the processor on the same chip. SRAM Cache,
which occupies most part of chip area, reduces processor-
memory interaction time and improves performance as access
time of DRAM is much higher compared to SRAM. In low
power applications, SRAM is preferred due to low standby
power dissipation compared to high magnitudes of refresh
current in DRAM. The standard 6T SRAM suffers from read
and write failures [1-2]. Read failure occurs due to voltage Fig. 1. Proposed 7T SRAM cell
distribution between pull-down transistor and access transistor The distinct part of the proposed design is separate read
while write failure occurs when the node storing ‘1’ discharges and write bit lines and the series connected tail transistor. This
through the access transistor. tail transistor is used for reducing the static power dissipation
To overcome these failures, many topologies have been and also as a 2T buffer for a read operation with NM4
discussed earlier [3-10]. In this paper, the proposed design is transistor. To further reduce the power dissipation, bit cell is
compared with standard 6T SRAM and low power (LP) 7T cut off from the ground during a write operation.

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 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), 16-19 October 2016, Abu Dhabi, UAE

The working of the proposed cell can be divided into three III. SIMULATION RESULTS
parts; namely hold, read and write operations. These
operations are explained as follows: To calculate the read, hold and write noise margins, a
sweeping method is used [1], in which one node (say node_1)
A. Hold Operation: is swept from 0 to VDD and corresponding values at the other
For hold state, write word line (WWL) is made low and node (node_2) is plotted to obtain voltage transfer
chip select (CS) is made high. If node_1 is holding ‘0’, then characteristic (VTC) curve. The same operation is repeated and
transistor NM0 would be off and transistor PM0 would be on node_2 is swept from 0 to VDD and the corresponding VTC at
and hence node_2 will be connected to supply voltage level/ node_1 is plotted on the same graph. Finally the two VTC
logic high (VDD). This, in turn, would turn off PM1, which curves, which are also called as butterfly plots are obtained
cuts off node_1 from VDD, hence a zero is maintained at with two lobes. Read and hold SNM are calculated as the side
node_1. The operation for holding ‘1’ can also be discussed in of the smallest square of the two largest squares that can be
the same way. drawn in the two lobes. The WSNM butterfly plot is different
compared to Read and Hold SNM curves and has only one
B. Read Operation: square. WSNM is the length of the side of the largest square
The read operation in standard 6T SRAM fails as the drawn at the bottom of butterfly plot.
operating voltage is scaled down because of the voltage
division between the access transistor and the pull-down A. Write SNM
transistor. In the proposed structure this case is not possible as To calculate WSNM of the proposed design, WWL is
a different single ended two transistors read buffer is used for made high and CS as low and the bit lines are pre-charged
reading. For a read operation, RBL bit line is pre-charged to accordingly to write ‘1’ or ‘0’ at node_1. Fig. 2 and Fig. 3
VDD and CS is also made high. If node_1 contains logical show the butterfly plots for the proposed design. In the same
‘0’, then RBL bit line discharges through NM4 and NM5, way the butterfly plot of standard 6T SRAM and LP 7T SRAM
which is sensed by the sense amplifier and indicate a read ‘0’ is also obtained.
operation. However if node_1 contains logical ‘1’, then RBL
bit line will have no path to discharge and will therefore stay SNM calculation for write ‘1’ and write ‘0’ is put up in
at VDD thereby indicating a read ‘1’ operation. The same will Table-I for the proposed design and other cells. It shows that
then be sensed by the sense amplifier justifying read ‘1’ the proposed design has an increase of 78% over the standard
operation. 6T for writing ‘1’ and 48% over standard 6T for writing ‘0’.
The SNM values of the proposed design is lesser than that of
C. Write Operation: LP 7T as the proposed design uses only one virtual ground
Write operation for the proposed 7T SRAM cell is unlike the LP 7T design, which has 2 virtual grounds.
same as that of standard 6T cell. Both the bit lines, WBL and
WBLB are pre-charged to the corresponding values and then
WWL is asserted. To write ‘1’ at node_1 which already has a
‘0’ stored, WBL is pre-charged to VDD and WBLB is
connected to ground. When the word line is asserted, transistor
NM0 would turn ON and node_2 is pulled to low level
(ground). This in turn would force PM1 to turn ON and
subsequently VDD is transferred to node_1. On the similar
ground, a write ‘0’ operation is performed.
In proposed 7T SRAM design, the stacking effect
[10-11] is generated due to the connection of source terminal
of pull-down transistors to the drain of the tail transistor NM5.
The stacking effect provided by NM0, NM1 and NM5 results
in lowering (negative) Vgs, negative Vbs and reduction in Vds
which subsequently reduces the power dissipation. Due to the
positive node voltage, three effects are observed. First the
voltage Vgs of transistor NM0 and NM1 becomes negative
which reduces the sub-threshold leakage current. Second, the Fig. 2. Combined WSNMs of write ‘1’ Standard 6T, LP 7T and the proposed
voltage Vbs of transistor NM0 and NM1 also reduces which 7T SRAM bit cells.
increases the threshold voltage and subsequently reduces the TABLE I. Comparison of Noise Margins of all cells.
sub-threshold leakage current [12]. Third the voltage Vds of WSNM WSNM RSNM Hold SNM
transistor NM0 and NM1 decreases which increases the SRAM Cell
’1’ (mV) ’0’(mV) (mV) (mV)
threshold voltage and reduces the sub-threshold leakage Standard 6T 330 330 200 450
current. The relationship [13] of sub-threshold current on these LP 7T 760 630 436 481
three parameter results in reduced power dissipation. Proposed 7T Cell 585 490 444 487.5

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 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), 16-19 October 2016, Abu Dhabi, UAE

pictorially by measuring the length of the largest square that

can be inscribed inside the smallest lobe of the butterfly curve.

Fig. 3. Combined WSNMs of write ‘0’ of Standard 6T, LP 7T and Proposed 7T

SRAM bit cells

B. Read SNM Fig. 5. Combined Hold SNMs of Standard 6T, LP 7T and the proposed 7T
SRAM bit cells.
Read SNM (RSNM) is defined as the noise voltage added
till the contents of the nodes remain unaltered during read D. Power Dissipation
operation. Hence for a reliable SRAM bit cell, high RSNM is
desired. RSNM is calculated pictorially by measuring the TABLE II. Comparison of power dissipations of all cells.
length of the largest square that can be inscribed inside the
Static Power Dynamic Power
smallest lobe of the butterfly curve. To calculate RSNM of SRAM Cell Operation
Dissipation Dissipation
proposed cell, read bit line (RBL) is pre-charged to VDD and Write 34.5 pW 328.2 nW
CS is given as VDD. Fig. 4 shows the butterfly plots using the Standard
Read 66.8 uW 921 nW
sweeping method as mentioned in the simulation setup. 6T
Hold 32.8 pW
Write 32.5 pW 100 nW
Read 0 39.05 pW
LP 7T 906.3 nW
Read 1 47.2 uW
Hold 29.8 pW
Write 30.6 pW 163.1 nW
Proposed Read 0 31.8 pW
906.4 nW
7T Cell Read 1 24.7 uW
Hold 28.8 pW

Power consumption is the major technical problem in

semiconductor memory. Off-state leakage is static power,
current that leaks through transistors even when they are turned
off while the dynamic power arises from the repeated
capacitance charge and discharge on the output of the gates.
Table-II presents the static power dissipation and dynamic
power dissipation for all the operations of write, read and hold
for standard 6T, LP 7T and the proposed 7T SRAM bit cells.
The proposed design shows better results than standard 6T
Fig.4. Combined RSNMs of Standard 6T, LP 7T and Proposed 7T SRAM bit and LP 7T as the former has only one virtual ground in
cells. comparison to the two virtual grounds for the latter. Static
power dissipation in proposed 7T SRAM is also lesser for all
C. Hold SNM operations compared to standard 6T and LP 7T SRAM cells.
Hold SNM (HSNM) is the amount of noise voltage that
can be added to the SRAM bit cell nodes such that the data E. Leakage Analysis:
stored cannot be altered while the cell is in an idle state. Fig. 5 The main components of leakage currents are ISUB, IG and
shows the Hold SNM using sweeping method after disabling IJN. The variation of leakage currents of bit cell with respect to
the write bit lines and read bit line. HSNM is calculated temperature variation is also simulated. ISUB varies from 6pA

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 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), 16-19 October 2016, Abu Dhabi, UAE

to 52pA while IG varies from 75fA to 132fA for a temperature taken from the RBL bit line. The sense amplifier is constructed
range of 25ºC to 150ºC. ISUB increases exponentially with the using differential amplifier which detects the differential
increase in temperature due to its dependence on VT (= kT/q). voltage between the inputs and a full swing output is obtained.
Fig. 7 shows that W_R signal is given as logic ‘1’ to perform
F. Proposed 7T SRAM Bit Cell Write Operation: read operations. Nodes node_1 and node_2 were given a series
of complemented inputs. The inputs are then read from the bit
Fig. 6 shows the waveform of the write operation for cell only when the select enable (SE) signal is activated.
proposed 7T SRAM cell.
IV. CONCLUSION
In this paper, a modified 7T SRAM has been proposed
which shows better results in terms of SNM and dynamic write
power in comparison to standard 6T and LP 7T SRAM cells.
The proposed 7T SRAM uses only one virtual ground which
reduces the power dissipation and other overhead in
comparison to multiple virtual grounds of other cell design.
The proposed work is therefore suitable for low power
application and has a potential application in battery operated
devices. The design can be further improved by operating the
cell at lower voltage and obtaining much higher stability.

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