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Assignment 3 - HDL for Counter Design

The document presents a Verilog HDL implementation of a MOD-5 up-counter using JK flip-flops, detailing the code structure, testbench, and simulation results. It describes the functionality of the counter, including how the bits toggle based on clock edges and enable signals, and emphasizes the asynchronous reset feature. The design is validated through a testbench that confirms its operational accuracy at a 100 MHz clock frequency, showcasing effective modular design and logic gating.

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Hakimi Rifhan
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2 views8 pages

Assignment 3 - HDL for Counter Design

The document presents a Verilog HDL implementation of a MOD-5 up-counter using JK flip-flops, detailing the code structure, testbench, and simulation results. It describes the functionality of the counter, including how the bits toggle based on clock edges and enable signals, and emphasizes the asynchronous reset feature. The design is validated through a testbench that confirms its operational accuracy at a 100 MHz clock frequency, showcasing effective modular design and logic gating.

Uploaded by

Hakimi Rifhan
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Assignment 3 - HDL for counter design

EEE3822-1: Digital System


Assoc Prof. Dr Maryam binti Isa
23rd June 2025

Muhammad Rifhan Hakimie bin Rosli


225361
MOD-5 UP counter using JK flip-flop

Verilog HDL code


// ASSIGNMENT 3 - HDL for MOD 5 UP COUNTER
// 225361
// MUHAMMAD RIFHAN HAKIMIE BIN ROSLI
`timescale 1ns/1ps

//-----------------------------------------------------------------------------
// Module: mod5upcounter
//-----------------------------------------------------------------------------
module mod5upcounter (
input wire clk,
input wire rst,
input wire z,
output wire b0,
output wire b1,
output wire b2
);

wire a0, a1, a2;

assign b0 = a0;
assign b1 = a1;
assign b2 = a2;

wire j0, k0, j1, k1, j2, k2;

assign j0 = z & ~a2;


assign k0 = z;

assign j1 = z & a0;


assign k1 = z & a0;

assign j2 = z & a1 & a0;


assign k2 = z;
// Three JK-FF instances
jk_ff ff0 (
.clk(clk),
.rst(rst),
.j(j0),
.k(k0),
.q(a0)
);

jk_ff ff1 (
.clk(clk),
.rst(rst),
.j(j1),
.k(k1),
.q(a1)
);

jk_ff ff2 (
.clk(clk),
.rst(rst),
.j(j2),
.k(k2),
.q(a2)
);

endmodule

//-----------------------------------------------------------------------------
// Module: jk_ff
//-----------------------------------------------------------------------------
module jk_ff (
input wire clk, // rising-edge clock
input wire rst, // async reset, active-low
input wire j, // J input
input wire k, // K input
output reg q // output
);

always @(posedge clk or negedge rst) begin


if (!rst)
q <= 1'b0;
else begin
case ({j,k})
2'b00: q <= q; // hold
2'b01: q <= 1'b0; // reset
2'b10: q <= 1'b1; // set
2'b11: q <= ~q; // toggle
endcase
end
end

endmodule
RTL Schematic
Testbench code
`timescale 1ns/1ps

module tb_mod5upcounter;

// Testbench signals
reg clk;
reg rst;
reg w;
wire b0, b1, b2;

// Instantiate the Unit Under Test (UUT)


mod5_upcounter uut (
.clk(clk),
.rst(rst),
.w(w),
.b0(b0),
.b1(b1),
.b2(b2)
);

// Clock generation: 100 MHz clock period = 10 ns


initial begin
clk = 0;
forever #5 clk = ~clk;
end

initial begin
// Initialize
rst = 0;
w = 0;
#10 rst = 1;
#10 w = 1;
#100;
w = 0;
#30;
w = 1;
#60;
// Finish simulation
$finish;
end

endmodule
Testbench waveform

Discussion
The Verilog source code implements a 3-bit MOD-5 up-counter by instantiating
three JK flip-flop modules connected with combinational logic that controls each J/K
input. In this design, the least significant bit toggles on each rising edge of the clock
when the enable is stated and the counter fails to reach its terminal state; the middle bit
toggles solely when the LSB is high, and the most significant bit toggles exclusively
during the transition from 011 to 100, thereby ensuring the correct five-state sequence
of 000→001→010→011→100→000. The reset is managed asynchronously, therefore
asserting the active-low reset instantaneously sets all outputs to 000, independent of
the clock, while releasing the reset restores the counter to its starting position.

The RTL diagram accurately represents this configuration: three designated


`jk_ff` blocks utilize a shared clock and reset, while logic gates supply their J and K
inputs based on the Boolean expressions in the code. An inverter on the MSB input path
inhibits the LSB from toggling during counter rollover, whereas AND gates guarantee
that the middle bit toggles alone when the preceding bit is high, and the MSB toggles
exclusively when both lower bits are high. All internal networks correspond directly to
the module outputs, verifying the absence of undesired feedback or combinational
loops beyond the designated JK functionality.

The simulation utilizing the supplied testbench—with a 100 MHz clock, regulated
reset pulses, and enable gating—confirms functional accuracy and timing integrity.
Upon reset, all outputs instantaneously revert to 000 and remain in that state until the
reset is triggered. When the enable signal is high, the counter progresses smoothly
through its five stages with each clock edge; when the enable signal is low, the outputs
maintain their last value, illustrating effective gating of all J/K inputs. Resuming enable
assertion maintains the sequence without disruptions or stability, verifying that the
design satisfies the 10 ns clock-period requirement and operates reliably under all
tested situations.
​
Conclusion​
​ The MOD-5 up-counter design effectively fulfills the assignment requirements.
The Verilog code uses particular, modular instantiation of JK flip-flops with explicitly
stated combinational logic for each J/K input, guaranteeing a dependable 5-state
sequence. The RTL diagram validates this configuration, demonstrating clear signal
routing and accurate logic gating. The testbench waveform ultimately confirms
functional accuracy under both reset and gated-enable settings, exhibiting reliable
performance at 100 MHz. This experiment demonstrates the efficacy of JK flip-flops in
small-scale counters and emphasizes optimal techniques in modular design, schematic
verification, and waveform validation.

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