USN 22BEE13

First/Third Semester B.E. / B.Arch. Semester End Examination, January-March 2022-23

Instructions: 1. From Part A answer any 5 questions each Question Carries 6 Marks.
2. From Part B answer any one full question from each unit and each
Question Carries 10 Marks.
3. From Part C answer any one full question and each Question Carries
20 Marks.

PART A
Answer any Five. L CO PO M
Explain the behaviour of a semiconductor diode under forward and reverse
1. (L2) (1) (1) (6)
bias conditions with necessary characteristics.
2. Draw the circuit of a Halfwave rectifier with C filter and explain its working. (L2) (1) (1) (6)
Sketch the output characteristics of a BJT in common emitter configuration.
3. (L2) (2) (1) (6)
Mark the different regions of operations and explain.
4. List the differences between BJT and FET. (L2) (1) (1) (6)
5 Explain the operation of an n-channel JFET using drain characteristics. (L2) (1) (1) (6)
Explain the following operational amplifier parameters with necessary
6. (L2) (3) (1) (6)
equations: (a) CMRR (b) Slew rate.
7. State and prove the two De Morgan’s theorems. (L2) (4) (1) (6)
PART B (minimum L3 level questions)
UNIT - I L CO PO M
8 a. Calculate the current through 48Ω resistor in the circuit shown in Figure 1.
(i) Assuming ideal diode
(ii) Assuming silicon diode with forward resistance of 1Ω.
Draw the equivalent circuit in each case.

Fig.1
(L3) (1) (1) (10)
OR
9 a. A 5V stabilized power supply is required to be produced from a 12V DC power supply input
source. The maximum power rating PZ of the zener diode is 2W.
(i) Propose a circuit using Zener diode to meet the requirement.
(ii) Explain the operation with necessary equations.
(L3) (1) (1) (10)

UNIT – II L CO PO M
10 a. Design a fixed bias circuit from the load line given in the Figure 2. Explain the design procedure in
detail.
Note: L (Level),CO (Course Outcome), PO (Programme Outcome), M (Marks)
 Fig.2
(L3) (2) (1) (10)
OR
11 a. What are the issues with respect to stability of operating point for a fixed bias circuit? Can you
suggest a way in order to improve the stability concerns?
(L3) (2) (1) (5)
b. In a common base connection as shown in Figure 3, α = 0.95. The voltage drop across 2 kΩ
resistance which is connected in the collector is 2V. Find the base current.

Fig.3
(L3) (2) (2) (5)
UNIT - III L CO PO M
12 a. The partial datasheet for a JFET indicates that typically I DSS = 9mA and VP = – 8V. Using these
values, determine the drain current for VGS = – 1V and – 4 V.
(L3) (1) (1) (5)
b. For the JFET in Figure 4, VP = – 4V and IDSS = 12 mA. Determine the minimum value of VDD
required putting the device in the constant-current region of operation.

Fig.4
(L3) (1) (2) (5)
OR
13 a. For the transfer characteristic curve of a JFET shown in Figure 5, write the equation for drain
current.
Note: L (Level),CO (Course Outcome), PO (Programme Outcome), M (Marks)
 Fig.5
(L3) (1) (1) (5)
b. Determine the value of drain current for the circuit shown in Figure 6.

Fig.6
(L3) (1) (1) (5)
UNIT - IV L CO PO M
14 a. Design an amplifier using opamp to provide a voltage gain of 26 dB.
(L3) (3) (2) (5)
b. A 20mV peak sine waveform voltage is applied to an op amp with Rf (feedback resistor) = 10 K
and R1 = 1 K inverting. Sketch the output waveform.
(L3) (3) (1) (5)
OR
15 a. Design a DAC using op-amp for four-bit input.
Obtain the output voltage when input applied to the DAC is:(i) 1001 (ii) 1111
(L3) (3) (2) (10)
UNIT -V L CO PO M
16 a. (a) Convert (4356.763)10 to its hexadecimal equivalent.
(b) Convert (1010011011.1101001)2 to its hexadecimal equivalent.
(L3) (4) (1) (5)
b. Represent (–24)10 in signed magnitude representation, 1’s complement and 2’s complement using
8-bits.
(L3) (4) (1) (5)
OR
17 a. Apply DeMorgan’s theorem and simplify the following expression: (A  C)(AB)
(L3) (4) (1) (5)
b. Simplify the following expression and implement using NAND gates only: XYZ  YZ  Z
(L3) (4) (1) (5)
Note: L (Level),CO (Course Outcome), PO (Programme Outcome), M (Marks)
 PART C L CO PO M
18 a. It is required to design a regulated DC power supply. Identify the various
blocks that are required to be included for the design. Explain the
significance of each block.
(L4) (1) (1) (10)
b. Further specify the requirements for each block in question 18 a. to
realize a 5 V DC power supply.
(L4) (1) (2) (10)
OR
19 a. Analyze the circuit shown in Figure 7 and obtain the expression for the
output voltage in terms of input voltages and resistors.

Fig. 7
(L4) (3) (2) (10)
b. For the circuit shown in Figure 7, evaluate the values of the resistors to
obtain the output voltage given by:
vo= – 6.67va + 12vb – 3vc.
(L4) (3) (2) (10)

Note: L (Level),CO (Course Outcome), PO (Programme Outcome), M (Marks)