Ex.No.

-1 ADDER AND SUBTRACTOR & CODE

CONVERTOR

AI
M: To design and construct half adder, full adder, half
subtractor and full subtractor circuits and verify
the truth table using logic gates.

APPARATUS REQUIRED:
SL.N COMPONE SPECIFICATI QTY
O. NT ON .
1. AND GATE IC 7408 1
2. X-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
4. OR GATE IC 7432 1
5. IC TRAINER KIT - 1
6. PATCH CORDS - 23

THEORY:

HALF ADDER:
A half adder has two inputs for the two bits to be added
and two outputs one from the sum ‘ S’ and other from the
carry ‘ c’ into the higher adder position. Above circuit is called
as a carry signal from the addition of the less significant bits
sum from the X-OR Gate the carry out from the AND gate.

FULL ADDER:
A full adder is a combinational circuit that forms the
arithmetic sum of input; it consists of three inputs and two
outputs. A full adder is useful to add three bits at a time but a
half adder cannot do so. In full adder sum output will be taken
from X-OR Gate, carry output will be taken from OR Gate.

HALF SUBTRACTOR:
The half subtractor is constructed using X-OR and AND
Gate. The half subtractor has two input and two outputs. The
outputs are difference and borrow. The difference can be
applied using X-OR Gate, borrow output can be implemented
using an AND Gate and an inverter.

FULL SUBTRACTOR:
The full subtractor is a combination of X-OR, AND, OR, NOT
Gates. In a full subtractor the logic circuit should have three
inputs and two outputs. The two half subtractor put together
gives a full subtractor .The first half subtractor will be C and A
B. The output will be difference output of full subtractor. The
expression AB assembles the borrow output of the
half subtractor and the second term is the inverted difference
output of first X-OR.

HALF ADDER
TRUTH
TABLE:

A B CARR SUM
Y

0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

K-Map for SUM: K-Map for CARRY:

1
1

SUM = A’B + AB’ CARRY = AB

LOGIC DIAGRAM:

FULL ADDER
TRUTH TABLE:

A B C CARR SU
Y M

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

K-Map for SUM

1
1

1 1

SUM = A’B’C + A’BC’ + ABC’ +

ABC K-Map for CARRY

CARRY = AB + BC
+ AC LOGIC DIAGRAM:
FULL ADDER USING TWO HALF ADDER
 HALF SUBTRACTOR

TRUTH TABLE:
A B BORRO DIFFEREN
W CE

0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

K-Map for DIFFERENCE

DIFFERENCE = A’B + AB’

K-Map for BORROW

BORROW =
A’B
LOGIC DIAGRAM
 FULL SUBTRACTOR

TRUTH TABLE:

BORR
A B C O DIFFEREN
W CE

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

K-Map for Difference

1 1

1 1

Difference = A’B’C + A’BC’ + AB’C’

+ ABC K-Map for Borrow

Borrow = A’B + BC + A’C

LOGIC DIAGRAM:

FULL SUBTRACTOR USING TWO HALF

SUBTRACTOR

PROCEEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:
 CODE CONVERTOR

AI
M:
To design and implement 4-bit
(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter

APPARATUS REQUIRED:
SL.N COMPONEN SPECIFICATI QTY
O. T ON .
1 X-OR GATE IC 7486 1
.
2 AND GATE IC 7408 1
.
3 OR GATE IC 7432 1
.
4 NOT GATE IC 7404 1
.
5 IC TRAINER KIT - 1
.
6 PATCH CORDS - 35
.

THEORY:

The availability of large variety of codes for the same

discrete elements of information results in the use of different
codes by different systems. A conversion circuit must be
inserted between the two systems if each uses different codes
for same information. Thus, code converter is a circuit that
makes the two systems compatible even though each uses
different binary code.

The bit combination assigned to binary code to gray

code. Since each code uses four bits to represent a decimal
digit. There are four inputs and four outputs. Gray code is a
non-weighted code.

The input variable are designated as B3, B2, B1, B0 and

the output variables are designated as C3, C2, C1, Co.
from the truth table, combinational circuit is designed. The
Boolean functions are obtained from K-Map for each output
variable.

A code converter is a circuit that makes the two systems

compatible even though each uses a different binary code. To
convert from binary code to Excess-3 code, the input lines must
supply the bit combination of elements as specified by code and
the output lines generate the corresponding bit combination of
code. Each one of the four maps represents one of the four
outputs of the circuit as a function of the four input variables.
 A two-level logic diagram may be obtained directly
from the Boolean expressions derived by the maps. These
are various other possibilities for a logic diagram that
implements this circuit. Now the OR gate whose output is C+D
has been used to implement partially each of three outputs.

BINARY TO GRAY CODE CONVERTOR

TRUTH TABLE:

Binary Gray Code

Input Output
B B B1 B0 G3 G2 G1 G
3 2 0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

K-Map for G3

G 3 = B3
K-Map for G2

K-Map for G1

K-Map for G0

LOGIC DIAGRAM:
 GRAY CODE TO BINARY CONVERTOR

TRUTH TABLE:

GRA
Y BINARY CODE
COD
E
G G2 G1 G0 B3 B2 B B
3 1 0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1

K-Map for B3:

B3 = G3
K-Map for B2:

K-Map for B1:

K-Map for B0:

LOGIC DIAGRAM:

BCD TO EXCESS-3
TRUTH CONVERTOR
TABLE: Excess –
3
| BCD input | output |

B B2 B1 B G3 G2 G1 G0
3 0
0 0 0 0 0 0 1 1

0 0 0 1 0 1 0 0

0 0 1 0 0 1 0 1

0 0 1 1 0 1 1 0

0 1 0 0 0 1 1 1

0 1 0 1 1 0 0 0

0 1 1 0 1 0 0 1

0 1 1 1 1 0 1 0

1 0 0 0 1 0 1 1

1 0 0 1 1 1 0 0

1 0 1 0 x x x x

1 0 1 1 x x x x
 1 1 0 0 x x x x
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x X

K-Map for E3:

E3 = B3 + B2 (B0 + B1)

K-Map for E2:

K-Map for E1:

K-Map for E0:

EXCESS-3 TO BCD

CONVERTOR TRUTH TABLE:

Excess – 3 BCD
| Input | Output |

B3 B2 B1 B G3 G2 G1 G0
0

0 0 1 1 0 0 0 0

0 1 0 0 0 0 0 1

0 1 0 1 0 0 1 0

0 1 1 0 0 0 1 1

0 1 1 1 0 1 0 0

1 0 0 0 0 1 0 1

1 0 0 1 0 1 1 0

1 0 1 0 0 1 1 1

1 0 1 1 1 0 0 0

1 1 0 0 1 0 0 1
LOGIC DIAGRAM:

EXCESS-3 TO BCD CONVERTOR

K-Map for A:

A = X1 X2 + X3 X4 X1

K-Map for B:
K-Map for C:

K-Map for D:

EXCESS-3 TO BCD CONVERTO

 PROCEDURE:

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table
(iii) Observe the logical output and verify with the truth
tables.

RESULT:
 Ex.No 2.-DESIGN OF MULTIPLEXER AND
DEMULTIPLEXER

AIM:

To design and implement the multiplexer and

demultiplexer using logic gates and study of IC 74150
and IC 74154.

APPARATUS REQUIRED:

SL.NO COMPONE SPECIFICATI QTY

. NT ON .
1. 3 I/P AND GATE IC 7411 2
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
2. IC TRAINER KIT - 1
3. PATCH CORDS - 32

THEORY:

MULTIPLEXER:
Multiplexer means transmitting a large number of
information units over a smaller number of channels or lines.
A digital multiplexer is a combinational circuit that selects
binary information from one of many input lines and directs it
to a single output line. The selection of a particular input line

n
is controlled by a set of selection lines. Normally there are 2
input line and n selection lines whose bit combination

determine which
input is selected.

DEMULTIPLEXER:
The function of Demultiplexer is in contrast to
multiplexer function. It takes information from one line and
distributes it to a given number of output lines. For this
reason, the demultiplexer is also known as a data distributor.
Decoder can also be used as demultiplexer.
In the 1: 4 demultiplexer circuit, the data input line goes
to all of the AND gates. The data select lines enable only one
gate at a time and the data on the data input line will pass
through the selected gate to the associated data output line.
 4:1 MULTIPLEXER

BLOCK DIAGRAM FOR 4:1

MULTIPLEXER:

FUNCTION TABLE:
S S INPUTS Y
1 0
0 0 D0 → D0 S1’ S0’
0 1 D1 → D1 S1’ S0
1 0 D2 → D2 S1 S0’
1 1 D3 → D3 S1 S0

Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’

+ D3 S1 S0 TRUTH TABLE:

S S Y =
1 0 OUTPUT
0 0 D0
0 1 D1
1 0 D2
1 1 D3
CIRCUIT DIAGRAM FOR MULTIPLEXER:

1:4 DEMULTIPLEXER

BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

FUNCTION TABLE:

S S INPU
1 0 T
0 0 X → D0 = X S1’
S0’
0 1 X → D1 = X S1’
S0
1 0 X → D2 = X S1
S0’
1 1 X → D3 = X S1 S0

Y = X S1’ S0’ + X S1’ S0 + X S1 S0’ + X S1 S0

 TRUTH TABLE:

INPU OUTPU
T T
S S0 I/ D D D D
1 P 0 1 2 3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1

LOGIC DIAGRAM FOR DEMULTIPLEXER:

PIN DIAGRAM FOR IC 74150:

PIN DIAGRAM FOR IC 74154:

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:
Ex.No.-3 Design of Encoders and Decoders

Theory

Encoder
Encoder is a combinational logic circuit that performs a reverse decoder
function. i.e, An Encoder accepts an active level on one of its inputs representing
a digit such as a decimal (or) octal and converts it to a coded output lines such
as binary or BCD. An encoder has 2n (or less) input lines and n output lines.

It’s generally represented as m-to-n line encoder (or) (m x n) encoder

where, m≤2n

Block Diagram
I0 mxn A0
I1 . (or) m A1
. n ..
. .
In-1 Encoder An-1

8 to-3 Encoder
8x3 Encoder
Block
Diagram

D0 A
D1 8x3 B
. Encod
.
D7 . er C

Truth Table
Inputs Outputs
D7 D6 D5 D4 D3 D2 D1 D0 A B C

0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1
Logic Diagram

D7 D6 D5 D4 D3 D2 D1 D0

A=D4+D5+D6+D7

B=D2+D3+D6+D7

Components Required
Digital trainer kit, IC7411 (3 i/p AND gate), IC7432 (OR gate), IC7404
(NOT gate), and connecting wires.

PROCEDURE
1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to Vcc .
3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.

C=D1+D3+D
Theory
Decode
r
A binary code of ‘n’ inputs can be represented as 2 n (or less) Min terms.
Decoder is a combinational logic circuit that accepts a set of inputs that
represents a binary number and activates only the output that corresponds to
that input number. It’s generally represented as n-to-m line decoder (or) (n x m)
decoder where, m≤2n

Block Diagram
A0 nx D0
A1 m A inputs
. D1
. .. D
. . outputs
An-1 Dn-1 (only 1 o/p is active for each
i/p).
 Types
1.2-to-4 line decoder
2.3-to-8 line decoder
3.4-to-10 line decoder (or) Binary-to-decimal decoder.
3- to-8 Decoder (or) Binary-to-Octal decoder (or) 1-out-of 8
Decoder
n=3(inputs); m≤2n ; i.e., m=8(outputs).
The 3 inputs are decoded into 8 outputs, each output representing one of
the min terms. A particular application of this decoder would be a binary to octal
conversion. The 3 invertors provide the complement of the inputs and each one
of the AND gates generates the min terms

3-to-8 Decoder (or) 3x8 Decoder

Block Diagram

A 3x8 D0
B (or) . D1
3 8 .
C Decode .
r
 Truth Table

Inputs Outputs

A B C D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0

0 1 0 0 0 0 0 0 1 0 0

0 1 1 0 0 0 0 1 0 0 0

1 0 0 0 0 0 1 0 0 0 0

1 0 1 0 0 1 0 0 0 0 0

1 1 0 0 1 0 0 0 0 0 0

1 1 1 1 0 0 0 0 0 0 0
Logic Diagram
A B C

IC7404

A' B' C' IC7411

1 D0=A'B'C'
2
13 12

D1=A'B'C

D2=A'BC'

D3=A'BC

D4=AB'C'

D5=AB'C

D6=ABC'

D7=ABC
 Components Required
Digital trainer kit, IC7411 (3 i/p AND gate), IC7432 (OR gate), IC7404
(NOT gate), and connecting wires.

PROCEDURE
1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to Vcc .
3. Apply the inputs to the respective input pins.
Verify the output with the truth

RESULT
Ex.No.-4 DESIGN OF MAGNITUDE COMPARATOR
AIM

To design and implement the magnitude comparator using

MSI device.

APPARATUS REQUIRED:

SL.N COMPONENT SPECIFICATI QTY

O. ON .
1. AND GATE IC 7408 2
2. X-OR GATE IC 7486 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
4-BIT
5. MAGNITUDE IC 7485 2
COMPARATOR
6. IC TRAINER KIT - 1
7. PATCH CORDS - 30

THEORY:

The comparison of two numbers is an operator that

determine one number is greater than, less than (or) equal to
the other number. A magnitude comparator is a
combinational circuit that compares two numbers A and B
and determine their relative magnitude. The outcome of the
comparator is specified by three binary variables that
indicate whether A>B, A=B (or) A<B.

A = A3 A2 A1

A0 B = B3 B2

B1 B0

The equality of the two numbers and B is

displayed in a combinational circuit designated by
the symbol (A=B).

This indicates A greater than B, then inspect the

relative magnitude of pairs of significant digits starting
from most significant position. A is 0 and that of B is 0.

We have A<B, the sequential comparison can be

1 1
expanded as A>B = A3B3 + X3A2B2 +
 1 1 1
X3X2A1B1 + X3X2X1A0B0 A<B = A3 B3 +

1 1 1
X3A2 B2 + X3X2A1 B1 + X3X2X1A0 B0
The same circuit can be used to compare the relative
magnitude of two BCD digits. Where, A = B is expanded as,

A = B = (A3 + B3) (A2 + B2) (A1 + B1) (A0 + B0)

   

x3 x2 x1 x0

PIN DIAGRAM FOR IC 7485:

8-BIT MAGNITUDE COMPARATOR

LOGIC DIAGRAM:

TRUTH TABLE:

A B A> A= A<
B B B
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
0
0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0
1

0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1
0
PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:
Ex.No.-5 DESIGN AND IMPLEMENTATION OF
COUNTERS USING FLIP FLOP

AIM:

To design and implement synchronous and asynchronous

counter.

APPARATUS REQUIRED:

S.N NAME OF THE RANG QUANTI

O. APPARATUS E TY
1. Digital IC trainer kit 1
2. JK Flip Flop IC 7473 2
3. D Flip Flop IC 7473 1
4. NAND gate IC 7400 1
5. Connecting wires As
required

THEORY:
Asynchronous decade counter is also called as ripple
counter. In a ripple counter the flip flop output transition
serves as a source for triggering other flip flops. In other
words the clock pulse inputs of all the flip flops are triggered
not by the incoming pulses but rather by the transition that
occurs in other flip flops. The term asynchronous refers to the
events that do not occur at the same time. With respect to the
counter operation, asynchronous means that the flip flop
within the counter are not made to change states at exactly
the same time, they do not because the clock pulses are not
connected directly to the clock input of each flip flop in the
counter.
A counter is a register capable of counting number of
clock pulse arriving at its clock input. Counter represents the
number of clock pulses arrived. A specified sequence of states
appears as counter output. This is the main difference between
a register and a counter. There are two types of counter,
synchronous and asynchronous. In synchronous common clock
is given to all flip flop and in asynchronous first flip flop is
clocked by external pulse and then each successive flip flop is
clocked by Q or Q output of previous stage. A soon the clock of
second stage is triggered by output of first stage. Because of
inherent propagation delay time all flip flops are not activated
at same time which results in asynchronous operation.
PIN DIAGRAM FOR IC 7476:

CIRCUIT DIAGRAM:

TRUTH TABLE:
 LOGIC DIAGRAM FOR MOD - 10 RIPPLE
COUNTER:

TRUTH TABLE:

CLK QA QB QC Q
D
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 0 0 0
PIN DIAGRAM:

SYNCHRONOUS COUNTER

LOGIC DIAGRAM:

TRUTH TABLE:

OUTPUT
CLK DATA
QA QB QC QD
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1
PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:
Ex.No.-6 DESIGN AND IMPLEMENTATION OF SHIFT
REGISTER

AI
M:
To design and implement the following shift registers
(i) Serial in serial out
(ii) Serial in parallel out
(iii) Parallel in serial out
(iv) Parallel in parallel out

APPARATUS REQUIRED:

SL.N COMPONE SPECIFICATI QTY

O. NT ON .
1. D FLIP FLOP IC 7474 2

2. OR GATE IC 7432 1

3. IC TRAINER KIT - 1

4. PATCH CORDS - 35

THEORY:
A register is capable of shifting its binary information in
one or both directions is known as shift register. The logical
configuration of shift register consist of a D-Flip flop cascaded
with output of one flip flop connected to input of next flip flop.
All flip flops receive common clock pulses which causes the
shift in the output of the flip flop. The simplest possible shift
register is one that uses only flip flop. The output of a given
flip flop is connected to the input of next flip flop of the
register. Each clock pulse shifts the content of register one bit
position to right.

PIN DIAGRAM OF IC 7474:

 SERIAL IN SERIAL OUT

LOGIC DIAGRAM:

TRUTH TABLE:

CL Serial Serial
K In Out
1 1 0
2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
7 X 1

SERIAL IN PARALLEL

OUT LOGIC DIAGRAM:

 TRUTH TABLE:

OUTPUT
CLK DAT QA Q QC QD
A B

1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1

PARALLEL IN SERIAL

OUT LOGIC DIAGRAM:

TRUTH TABLE:

CLK Q Q Q Q0 O/
3 2 1 P
0 1 0 0 1 1

1 0 0 0 0 0

2 0 0 0 0 0

3 0 0 0 0 1

RESULT: