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StateMachines

The document discusses the fundamentals of state machines, focusing on JK flip-flops and their excitation tables. It outlines the process of sequential logic synthesis, including constructing state diagrams, excitation tables, and deriving boolean equations. Additionally, it provides an example of designing a 2-bit binary counter using D flip-flops and includes circuit implementation details.

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Mahesh Morla
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0 views10 pages

StateMachines

The document discusses the fundamentals of state machines, focusing on JK flip-flops and their excitation tables. It outlines the process of sequential logic synthesis, including constructing state diagrams, excitation tables, and deriving boolean equations. Additionally, it provides an example of designing a 2-bit binary counter using D flip-flops and includes circuit implementation details.

Uploaded by

Mahesh Morla
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Spring 2015 Week 6 Module 29

Digital Circuits and


Systems

State Machines 1

Shankar Balachandran*
Associate Professor, CSE Department
Indian Institute of Technology Madras

*Currently a Visiting Professor at IIT Bombay


JK Flipflop

CLK J K Q*
0 0 Q
0 1 0
1 0 1
1 1 Q

J: Set
K: Reset
J=K=0: Keep old value
J=K=1: toggle

Sequential Circuits 2
Example:

1. Input/Output logic equations:

J 0  Q1 X ; K 0  Q1 X ;
J1  X ; K 1  X  Q0  XQ0  X Q0

Analysis and Design of Sequential Logic Circuits 3


2. State table: 3. State Diagram:
J 0  Q1 X ; K 0  Q1 X ;
J1  X ; K 1  X  Q0  XQ0  X Q0
Present Next 0/- 0/-
Input Flip-flop Inputs Out
State State
X (none) 00 01
Q1 Q0 J1 K1 J0 K0 Q1* Q0*
0 0 0 0 1 0 0 0 0 0/-
1/-
0 0 1 0 0 0 0 0 1
0 1 0 0 1 1 0 0 1 1/- 1/-
11 10
0 1 1 0 0 1 0 1 1
0/- 1/-
1 0 0 1 0 0 0 1 0
1 0 1 1 1 0 0 1 1
1 1 0 1 0 0 1 1 0
1 1 1 1 1 0 1 0 0

Analysis and Design of Sequential Logic Circuits 4


Sequential Logic Synthesis
 Sequential network design is simply the inverse process
of sequential network analysis:
1. Construct a state diagram
2. Choose a set of state variables and assign state-variable
combinations to the named states in the state diagram.
3. Construct the excitation table: For a given transition from a
present state to its next state, this table indicates the inputs that
must be applied to the flip-flops.
4. Derive the boolean equations for flip-flop excitation and the
explicit outputs.
5. Draw a logic diagram to implement the above equations using
logic gates and flip-flops.

Analysis and Design of Sequential Logic Circuits 6


Flip-flop Excitation Tables

 Excitation tables for D and T flip-flops:


Q Q* D T
0 0 0 0
0 1 1 1
1 0 0 1
1 1 1 0
 Excitation table for JK flip-flop:

Q Q* J K J K
0 0 0 0 or 1 0 X
0 1 1 0 or 1 1 X
1 0 0 or 1 1 X 1
1 1 0 or 1 0 X 0

Analysis and Design of Sequential Logic Circuits 7


Example:

 Design a 2-bit binary counter using D flip-flops.

 State diagram:

00 01

11 10

Analysis and Design of Sequential Logic Circuits 8


 Excitation table:

Input Present State Next State Flip-flop Inputs Output


(none ) Q1 Q0 Q1* Q0* D1 D0 (none)
0 0 0 1 0 1
0 1 1 0 1 0
1 0 1 1 1 1
1 1 0 0 0 0

Analysis and Design of Sequential Logic Circuits 9


 Circuit implementation:

Analysis and Design of Sequential Logic Circuits 10


End of Week 6: Module 29

Thank You

Intro to State Machines 11

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