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Xcelium Tutorial

September 2019

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Xcelium Tutorial
Before going to next steps, please note that those lines that start with ‘#’ are explanation, lines that follow
with ‘$’ are commands and you need to copy and then paste in your terminal and press enter.

1. RTL simulation
In this part, you only need the verilog code (RTL) “alu_conv.v” and its testbench “alu_conv_test.v”.

1) # Go into the directory “Lab1”. This is the directory you create in Genus_Tutorial. And copy alu_conv_test.v to this folder.
$ cd ./Lab1
$ cp /vol/ece303/genus_tutorial/alu_conv_test.v .
Lab1 folder should contain: alu_conv.v , alu_conv_test.v. You could type “ls” to see files in the directory.

(If you have not done Genus_Tutorial, you can simply run the following command to copy the files so you can still follow this
tutorial to learn Xcelium.
$ mkdir Lab1
$ cd ./Lab1
$ cp /vol/ece303/genus_tutorial/alu_conv.v .
)

2) # Enter the following commands to source the cadence environment

$ source /vol/ece303/genus_tutorial/cadence.env

3) # Type the following command to run the cadence tool. In this case you will see a new open window like this:
$ xrun -64bit -gui -access r alu_conv.v alu_conv_test.v

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Important: the terminal should show no error, or the new window will not pop-up.

4) # In this window you can select the signal you want to send to the Waveform Window (right click a signal -> Send to
Waveform Window)

5) # In the Waveform SimVison window you can simulate your design. Simulation->Run.
Note: You need to use zoom in/out function to pick the expected observation time period.

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Important: if you see error bellow, click “Reset the simulation back to time 0”. Then run simulation again.

6) # Verify the result of RTL code

Based on the observation, you can confirm whether the function is correct of your RTL code.
Right click column of Cursor to change value from Hex to Decimal or Binary, so that you can check whether the result is
correct.

Note: Close all windows when you finish this session.

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2. Gate level netlist simulation:

To do this part, you need to first finish the Genus lab. Check the other tutorial “Genus Tutorial”.
After you finish the Genus lab, you should have a new verilog file: alu_conv_syn.v under “Synthesis”
folder. (This is the gate level netlist file)

1) # Go into the directory “Lab1”

$ cd ./Lab1
2) # Enter the following commands to source the cadence environment
$ source /vol/ece303/genus_tutorial/cadence.env

3) # Type the following command to run the cadence tool.

$ xrun -64bit -gui -access r -xmelab_args "-warnmax 0 -delay_mode zero -maxdelays" ./Synthesis/alu_conv_syn.v
alu_conv_test.v /vol/ece303/genus_tutorial/NangateOpenCellLibrary.v
Important: the commands inside “” are options for “xmelab” which is an elaboration function called for gate level netlist
simulation. alu_conv_syn.v is the gate level netlist which was generated in genus tutorial.
Note: If you see error below, add one line
`timescale 1ns/10ps
at the top of alu_conv_syn.v file and enter command again. Generally, we need the above line for each Verilog file to be
simulated.

Add this line at the top of the file

After modification, save change and quit, then go back to setp 3 to type the same command.
4) After last command, there will be a SimVison window pop-up, in this window you can select the signal you want to send to
the Waveform Window (right click a signal -> Send to Waveform Window). Scroll down to the bottom and send signals in
alu_conv_test to waveform window.
In the Waveform SimVison window you can simulate your design. Simulation->Run.

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The result of the gate level simulations should match with the RTL simulations. But simulation is based on
gate level netlist this time.
Note in this tutorial, we did not give timing information to each gate, which means each gate has zero delay.
We can perform simulation with real delay of gate, which is called “back-annotated” simulation. This
operation needs to modify the xrun command. We skip this operation in this tutorial.

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