Scribd
Upload
0 views11 pages

Lab Report

The project report details the design and simulation of digital components using SystemC, including a full subtractor, a 4-bit ALU, and a multiplexer, implemented on the Zybo Z7-10 board. It covers new concepts such as behavioral and structural modeling, hardware deployment, and real-time interfacing. Additionally, it describes challenges faced during deployment and integration of hardware/software co-simulation frameworks, including a GCD calculator and a hardware-accelerated function.

Uploaded by

22119034
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
0 views11 pages

Lab Report

The project report details the design and simulation of digital components using SystemC, including a full subtractor, a 4-bit ALU, and a multiplexer, implemented on the Zybo Z7-10 board. It covers new concepts such as behavioral and structural modeling, hardware deployment, and real-time interfacing. Additionally, it describes challenges faced during deployment and integration of hardware/software co-simulation frameworks, including a GCD calculator and a hardware-accelerated function.

Uploaded by

22119034
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 11

Project Report

Project
HW/SW Final Project
Name
[1] Lê Công Đức 19119041
Student [2] Trần Hoàng Anh Tú ID 22119034
[3] Lương Anh Tài 22119030
Class Supervisor Assoc. Prof. Phan Van Ca

Do you verify that the code included with this report is your's original work
(YES/NO)? ________

A. DESIGN PROJECT

1. Summarize (in your own words) the subject of this project:


This project focuses on designing and simulating several digital components using SystemC
at both behavioral and structural levels. The components include a full subtractor, a 4-bit
ALU, and a 4-to-1 4-bit multiplexer. The final design was also implemented on the Zybo Z7-
10 development board, allowing real-time input via switches and output display through
LEDs.

2. Describe the new concepts covered in this project:


Behavioral modeling in SystemC for arithmetic and logic operations
Structural modeling by combining multiple lower-level components
Use of a testbench to validate digital designs
·Hardware deployment on Zybo board using hardware mapping techniques
Interfacing with physical switches and LEDs for embedded design verification
3. Describe how this project built upon previous ones:
This project extended the knowledge from previous labs by integrating multiple modules
into a complete system and deploying them in hardware. Earlier tasks introduced us to
designing individual components like multiplexers. In this project, those components were
reused and combined into more complex circuits, further reinforced with real-world
testing on the Zybo board.

4. Describe the most difficult part of this project for you:


he most challenging part was deploying the design on the Zybo board. Mapping the virtual
signals to physical hardware elements such as switches and LEDs required a deep
understanding of the Zybo's pin configurations and careful constraint file setup. Debugging
the real hardware behavior was also more time-consuming compared to simulation.

5. Describe problems you faced and how you solved them:


· Problem: Timing mismatches in simulation due to uninitialized signals.
Solution: Proper initialization of signals in the testbench and ensuring synchronization
using wait() in SystemC.
· · Problem: Mismatched input/output bit widths during ALU operation.
Solution: Added proper signal casting and ensured consistent 4-bit logic.
· · Problem: Incorrect pin mapping for Zybo deployment.
Solution: Reviewed Zybo Z7-10 reference manual and used correct .xdc constraints for
switches (SW0–SW7) and LEDs (LD0–LD3).
·

6. Submit your source code, testbench, and simulation output.


// alu_4bit.cpp
#include <systemc.h>

SC_MODULE(ALU4bit) {
sc_in<sc_uint<4>> A, B; // 4-bit inputs
sc_in<sc_uint<4>> op_code; // 4-bit operation selector
sc_out<sc_uint<4>> result; // 4-bit result
sc_out<bool> carry_borrow; // Carry or Borrow

void process() {
sc_uint<4> a = A.read();
sc_uint<4> b = B.read();
sc_uint<4> op = op_code.read();
sc_uint<4> res = 0;
bool cb = 0;

switch (op) {
case 0x0: // ADD
res = a + b;
cb = (a + b) > 15;
break;
case 0x1: // SUB
res = a - b;
cb = a < b; // borrow
break;
case 0x2: // INC A
res = a + 1;
cb = (a + 1) > 15;
break;
case 0x3: // DEC A
res = a - 1;
cb = (a == 0);
break;
case 0x4: // AND
res = a & b;
cb = false;
break;
case 0x5: // OR
res = a | b;
cb = false;
break;
case 0x6: // NAND
res = ~(a & b);
cb = false;
break;
case 0x7: // XOR
res = a ^ b;
cb = false;
break;
default:
res = 0;
cb = false;
}

result.write(res);
carry_borrow.write(cb);
}

SC_CTOR(ALU4bit) {
SC_METHOD(process);
sensitive << A << B << op_code;
}
};
// full_subtractor.cpp
#include <systemc.h>
SC_MODULE(FullSubtractor) {
sc_in<bool> A, B, Bin; // Inputs: A, B, Borrow-in
sc_out<bool> Diff, Bout; // Outputs: Difference, Borrow-out

void process_subtract() {
bool a = A.read();
bool b = B.read();
bool bin = Bin.read();

Diff.write(a ^ b ^ bin);
Bout.write((!a & b) | (!a & bin) | (b & bin));
}

SC_CTOR(FullSubtractor) {
SC_METHOD(process_subtract);
sensitive << A << B << Bin;
}
};
module ALU_4bit (
input [3:0] A,
input [3:0] B,
input [3:0] opcode,
output reg [3:0] result,
output reg carry_out
);

always @(*) begin


case (opcode)
4'b0000: {carry_out, result} = A + B; // ADD
4'b0001: {carry_out, result} = A - B; // SUB
4'b0010: {carry_out, result} = A + 4'b0001; // INC A
4'b0011: {carry_out, result} = A - 4'b0001; // DEC A
4'b0100: {carry_out, result} = {1'b0, A & B}; // AND
4'b0101: {carry_out, result} = {1'b0, A | B}; // OR
4'b0110: {carry_out, result} = {1'b0, ~(A & B)}; // NAND
4'b0111: {carry_out, result} = {1'b0, A ^ B}; // XOR
default: {carry_out, result} = 5'b00000;
endcase
end

endmodule

extern "C" void NN_DigitMult_SC(NN_DIGIT a[2], NN_DIGIT b, NN_DIGIT c)


{
dataI1.write(b);
dataI2.write(c);
enable_s.write(1);
wait(1, SC_NS);

while (!done_s.read()) {
wait(1, SC_NS);
}

a[0] = dataO1.read(); // low bits


a[1] = dataO2.read(); // high bits
enable_s.write(0);
wait(1, SC_NS);
}
void process() {
while (1) {
wait(); // Wait for 1ns
switch (exe_state.read()) {
case WAIT:
if (enable.read()) {
exe_state = EXECUTE;
}
break;
case EXECUTE:
temp = (sc_uint<64>)in_data_1.read() * (sc_uint<64>)in_data_2.read();
exe_state = OUTPUT;
break;
case OUTPUT:
out_data_low.write(temp.range(31, 0));
out_data_high.write(temp.range(63, 32));
done.write(1);
exe_state = FINISH;
break;
case FINISH:
if (!enable.read()) {
done.write(0);
exe_state = WAIT;
}
break;
}
}
}
int sc_main(int argc, char* argv[])
{
done_s = 0;
enable_s = 0;
dhdemo DH("DH");

nnDIGITmult multiplier("Hardware_Multiplier");
multiplier.enable(enable_s);
multiplier.in_data_1(dataI1);
multiplier.in_data_2(dataI2);
multiplier.out_data_low(dataO1);
multiplier.out_data_high(dataO2);
multiplier.done(done_s);

sc_start(2000000, SC_NS);
return 0;
}

7. Provide screenshots or photos demonstrating the working implementation of


this project.
B. HW/SW CO-SIMULATION
1. Summarize (in your own words) the subject of this project:
This project focuses on developing a hardware/software co-simulation framework using
SystemC. It includes two major tasks: (1) implementing a GCD calculator with software-
only and hardware/software partitioned versions, and (2) accelerating a computationally
expensive function (NN_DigitMult()) from the Netbench benchmark by designing a
hardware module and integrating it into a C-based software system.

2. Describe the new concepts covered in this project:


SW/SW’ and HW/SW partitioning in embedded systems

Handshake communication protocols between software and hardware modules

Finite State Machine (FSM) design for hardware task execution

Integration of SystemC hardware models with C code using extern "C"

Optimization of computation-heavy tasks through hardware acceleration

Benchmarking and measuring improvements in execution efficiency

3. Describe how this project built upon previous ones:

This project built on previous work involving SystemC module creation by introducing
concurrency and real-time HW/SW communication. We leveraged earlier modules such as
the GCD logic and expanded them with handshake protocols and FSMs for hardware
integration. The knowledge from ALU and multiplexer designs was essential for structuring
hardware logic efficiently

4. Describe the most difficult part of this project for you:


The hardest part was correctly integrating the SystemC hardware module with the existing
C benchmark code. Ensuring that NN_DigitMult() in software could seamlessly call the
hardware accelerator through the extern "C" bridge required careful management of data
types, memory pointers, and synchronization timing between hardware and software.

5. Describe problems you faced and how you solved them:


Problem: Deadlock in the handshake mechanism between software and hardware in GCD
module.
Solution: Reviewed the FSM logic and ensured proper signal deassertion after each
computation.

Problem: Data mismatch between C integers and SystemC ports.


Solution: Used sc_uint<32> and explicit casting to ensure compatibility.

Problem: Function call to hardware-accelerated NN_DigitMult() was not producing correct


output.
Solution: Verified data flow and corrected state transitions in FSM to ensure that outputs
were latched and read correctly by software.

6. Submit your source code, testbench, and simulation output.

gcd_sw.cpp, gcd_hw.cpp, gcd_testbench.cpp


digit.c and dh_mod.cpp (Netbench files)
SystemC hardware model for NN_DigitMult()
Simulation traces and output logs

7. Provide screenshots or photos demonstrating the working implementation of


this project.

You might also like