0% found this document useful (0 votes)
2 views4 pages

Study and Simulation of TFET

The document discusses the study and simulation of Tunnel Field-Effect Transistors (TFETs) as a next-generation MOS device, highlighting their potential to overcome limitations of traditional MOSFETs, particularly in terms of power dissipation and subthreshold swing. It explains the operational principles of TFETs, including their reliance on quantum-mechanical band-to-band tunneling for charge carrier injection, and presents analytical models for evaluating their performance. The findings suggest that effective TFET design requires consideration of tunneling probability and occupancy functions to optimize device characteristics.

Uploaded by

Vaishnavi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
2 views4 pages

Study and Simulation of TFET

The document discusses the study and simulation of Tunnel Field-Effect Transistors (TFETs) as a next-generation MOS device, highlighting their potential to overcome limitations of traditional MOSFETs, particularly in terms of power dissipation and subthreshold swing. It explains the operational principles of TFETs, including their reliance on quantum-mechanical band-to-band tunneling for charge carrier injection, and presents analytical models for evaluating their performance. The findings suggest that effective TFET design requires consideration of tunneling probability and occupancy functions to optimize device characteristics.

Uploaded by

Vaishnavi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 4

Study and Simulation of TFET: Next Generation

MOS Device
Amit Jarika, C.Charitha, Khemanand Bhagat Pankaj, Laukik Deshpande, V.G.Vijitha
Centre of VLSI and Nanotechnology (CVN), VNIT, Nagpur

Abstract—Progress of CMOS technology has been accomplished subthreshold swing beyond the 60-mV/dec limit of
by the downsizing of MOSFETs. However, it has been expected conventional MOSFETs. The problems of Tunnel-FET
that the downscaling will reach its limits about the gate length of
5 nm around the year of 2020. At nano-level power dissipation is
(TFET) devices has been rectified by taking extremely low
the fundamental problem. Scaling the supply voltage reduces the off-current resulting from their reverse biased gated p-i-n
energy needed for switching, but the field-effect transistors configuration and by the appealing possibility of achieving
(FETs) in today’s integrated circuits require at least 60mV of subthermal switching slopes owing to their quantum–
gate voltage to increase the current by one order of magnitude at
room temperature. This is why we have to look for some mechanical band-to-band tunneling (BTBT) carrier injection
alternative solution. Tunnel FETs avoid the voltage limit by using mechanism.
quantum-mechanical band-to-band tunneling, rather than
thermal injection, to inject charge carriers into the device
In order to overcome this issue, much research has been
channel. So integrating tunnel FETs with CMOS technology
could improve low-power integrated circuits. In this paper we are accomplished toward the improvement of the tunneling barrier
discussing Tunnel FET, its characteristics and band diagram transparency, namely, small-band-gap strained
which is simulated using the tool Sentaurus Device. heterostructures, light-effective-mass structures as III–V
compounds or CNTs and direct-band-gap semiconductors.
Keywords—TFET, Band to Band tunneling, device, Tcad.
With the same target of maximizing the tunneling probability,
nonconventional architectures featuring high-k gate dielectrics
I. INTRODUCTION and vertical tunnel devices have also been widely explored.

Reducing the size of MOSFETs has enabled extraordinary This paper explains the structure of a Tunnel FET and how it
improvements in the switching speed, density, functionality functions, and discusses subthreshold slope for both
and cost of microprocessors. As we move into nanoscale, we MOSFETs and Tunnel FETs.
have an electronic unit containing more components.
Consequently it results in consuming more energy and hence II. Device Structure and Operation
power consumption becomes a huge issue. However, it is very
difficult to lower supply voltage due to the transport
mechanism of traditional MOSFETs, which is governed by the
carrier diffusion over a thermal barrier. Even in the ideal case,
the sub-threshold swing of MOSFETs is limited by 60
mV/dec. Another issue that arises is the rising leakage currents
which degrade the switching ratio of ‘on’ and ‘off’ currents
(ION/IOFF). This highlights the need for new devices that can
compete with or complement CMOS transistors. Tunnel Field-
Effect Transistor is considered as a promising solution for the
above two limitations.

The transport mechanism of Tunnel Field-Effect Transistor


(Hereafter referred as TFET) is under quantum mechanics.
The working of a TFET is similar to a field-effect transistor The structure for single gate TFET is shown in the Fig. 1. The
(FET), where a change of gate voltage turns the current ON basic design is a gated p-i-n diode. The tunneling takes place
and OFF. But TFET uses band-to-band tunneling in their ON in this device between the intrinsic and p+ regions. To operate
state, as well as in the transition between the OFF and ON this device, the p-i-n diode is reverse biased. The source is
states. This device also has the potential for extremely low grounded and a positive voltage is applied to the drain and a
OFF current, and present the possibility to lower the voltage is applied to the gate. Without a gate voltage, the
width of the energy barrier between the intrinsic region and With a simple change of variables, the aforementioned integral
the p+ region is much wider and the device is in the OFF-state. can be expressed as a difference of complete Fermi integrals
As the positive gate voltage increases, the bands in the of order 0
intrinsic region are pushed down in energy, narrowing the
tunneling barrier and allowing tunneling current to flow.

III. Model and Equations

A general expression for the elastic tunneling current between


“originating region 1” and “destination region 2” is congruent
with

When the TFET operates in the ON state, the drain bias


controls both the channel conduction band and the electron
Where PT is the probability of penetrating the tunneling quasi-Fermi level at the source/channel interface so that
barrier and f and G are the Fermi–Dirac distribution and the dEFn,ch/dVDS = dCBch,min/dVDS = −1. In this work, the
density of states (DOS).Together with rigorously defined hole quasi-Fermi level of the source has been taken as
TFET compact models, several analytical approaches have reference for the energy (thus, EFp,s = 0 eV). This means that
been proposed, consisting of a simple BTBT generation the parameter β depends on the source degeneracy only, α and
formula that does not take into account the Fermi–Dirac δ linearly depend on VDS, and γ can be considered
distributions. It is the purpose of this letter to show, through a independent of the drain bias under the condition that both
study of the device output characteristics, that a proper CBch,min and EFn,ch decrease one-to-one for increasing
analytical model of TFETs would be even more accurate if, VDS.
besides the tunneling probability contribution, also the source
and channel occupancy functions are taken into account The tunneling current is assumed to be the dominant
contribution to the device drain current, it is straightforward to
A large tunneling current requires not only a tunneling barrier evaluate the output conductance derivative as
transparent enough but also the availability of carriers (at the
initial point of the tunneling event) and the availability of
empty states (at the end of the tunneling path) into which the
carriers can tunnel.
B. Tunneling Probability Contribution

A. Occupancy Probability Contribution The following approximate expression is used for calculating
tunneling probability:-
Relation between the tunneling current and the Fermi–Dirac
distributions

The tunneling barrier is perfectly transparent inside the


allowed tunneling energy window (i.e., PT {CBch,min < E < Where xh and xe are the spatial coordinates at the beginning
VBs,max} = 1) and zero if otherwise. and at the end of the tunneling path, respectively, and mr is the
reduced effective mass.
The total tunneling current (resulting from the two
contributions of current from the valence band to the empty
states of the conduction band and from the conduction band to
the empty states of the valence band as proportional to
IV. RESULTS AND DISCUSSION ii. VGS = 0.53V and VDS = 0V

1. Device:

2. Band Diagram:

i. VGS = 0V and VDS = 0V

iii. VGS = 0.53V and VDS = 0.53V


3. Output Characteristics: V. CONCLUSION

Hence, to understand the basic structure of Tunnel FET and to


get large tunneling current, it requires not only a tunneling
barrier transparent but also, has to consider the availability of
carriers (at the initial point of the tunneling event) and the
availability of empty states (at the end of the tunneling path)
into which the carriers can tunnel.
So, overall we come under conclusion that:-
1) The drain current of real TFETs cannot increase arbitrarily,
but there is a drain saturation voltage, after which the device
current becomes independent of the drain bias.
2) The modulation of the device current at the beginning of the
V DS sweep is mainly determined by a change in the
occupancy functions and it is almost independent of the
tunneling probability modulation.
3) The main cause of the super-linear output onset is not the
exponential dependence of the device current on the tunneling
path.
4) Apart from considering tunneling probability, analysis of
the occupancy function dependence on the bias has to be
necessarily taken into account.
5) The proper analytical model of TFETs would be even more
accurate if the tunneling probability contribution, source and
According to the degeneracy of the source Fermi level channel occupancy functions are taken into account.
(i.e., V Bs,max − EFp,s) and to the gate voltage (that affects
both EFp,s − CBch,min and EFn,ch − CBch,min), the TFET
ID−VDS curve assumes different shapes. We consider in the VI. REFERENCES
following that the channel conduction band energy at VDS
= 0 V is smaller than both V Bs,max and EFp,s by at least 1. Experimental demonstration of 100nm channel length
three times the thermal energy kBT. In0.53Ga0.47As-based vertical inter-band tunnel
field effect transistors (TFETs) for ultra low-power
1) V Bs,max > 3kBT that is the condition for a degenerate
logic and SRAM applications.
source. In this case, the drain current is linearly dependent on 2. A Simulation Approach to Optimize the Electrical
the drain-to-source voltage drop, since can be approximated as Parameters of a Vertical Tunnel FET by Krishna
ID ∝ −EFn,ch. Consequently, this case presents an output Kumar Bhuwalka, Jörg Schulze, Member, IEEE, and
conductance derivative proportional to Ignaz Eisele.
3. Understanding the Superlinear Onset of Tunnel-FET
Output Characteristic by Luca De Michielis, Student
Member, IEEE, Livio Lattanzio, and Adrian M.
2) V Bs,max < −3kBT that is the case with a nondegenerate Ionescu, Senior Member, IEEE.
4. Device Simulation of Tunnel Field Effect Transistor
source. Under this condition, both terms in (5) are equally
(TFET) by DAVID HUANG1, Hui Fang2, Ali
contributing in the output conductance derivative, and it Javey21Cerritos College; 2University of California,
reaches its maximum when EFn,ch = V Bs,max. Each term Berkeley
gives rise to one asymptote: the first with exponentially
increasing values for increasing VDS going from zero to
VDS = −V Bs,max/q and the other with exponentially
decreasing values for VDS > −V Bs,max/q.

You might also like