Study and Simulation of TFET
Study and Simulation of TFET
MOS Device
Amit Jarika, C.Charitha, Khemanand Bhagat Pankaj, Laukik Deshpande, V.G.Vijitha
Centre of VLSI and Nanotechnology (CVN), VNIT, Nagpur
Abstract—Progress of CMOS technology has been accomplished subthreshold swing beyond the 60-mV/dec limit of
by the downsizing of MOSFETs. However, it has been expected conventional MOSFETs. The problems of Tunnel-FET
that the downscaling will reach its limits about the gate length of
5 nm around the year of 2020. At nano-level power dissipation is
(TFET) devices has been rectified by taking extremely low
the fundamental problem. Scaling the supply voltage reduces the off-current resulting from their reverse biased gated p-i-n
energy needed for switching, but the field-effect transistors configuration and by the appealing possibility of achieving
(FETs) in today’s integrated circuits require at least 60mV of subthermal switching slopes owing to their quantum–
gate voltage to increase the current by one order of magnitude at
room temperature. This is why we have to look for some mechanical band-to-band tunneling (BTBT) carrier injection
alternative solution. Tunnel FETs avoid the voltage limit by using mechanism.
quantum-mechanical band-to-band tunneling, rather than
thermal injection, to inject charge carriers into the device
In order to overcome this issue, much research has been
channel. So integrating tunnel FETs with CMOS technology
could improve low-power integrated circuits. In this paper we are accomplished toward the improvement of the tunneling barrier
discussing Tunnel FET, its characteristics and band diagram transparency, namely, small-band-gap strained
which is simulated using the tool Sentaurus Device. heterostructures, light-effective-mass structures as III–V
compounds or CNTs and direct-band-gap semiconductors.
Keywords—TFET, Band to Band tunneling, device, Tcad.
With the same target of maximizing the tunneling probability,
nonconventional architectures featuring high-k gate dielectrics
I. INTRODUCTION and vertical tunnel devices have also been widely explored.
Reducing the size of MOSFETs has enabled extraordinary This paper explains the structure of a Tunnel FET and how it
improvements in the switching speed, density, functionality functions, and discusses subthreshold slope for both
and cost of microprocessors. As we move into nanoscale, we MOSFETs and Tunnel FETs.
have an electronic unit containing more components.
Consequently it results in consuming more energy and hence II. Device Structure and Operation
power consumption becomes a huge issue. However, it is very
difficult to lower supply voltage due to the transport
mechanism of traditional MOSFETs, which is governed by the
carrier diffusion over a thermal barrier. Even in the ideal case,
the sub-threshold swing of MOSFETs is limited by 60
mV/dec. Another issue that arises is the rising leakage currents
which degrade the switching ratio of ‘on’ and ‘off’ currents
(ION/IOFF). This highlights the need for new devices that can
compete with or complement CMOS transistors. Tunnel Field-
Effect Transistor is considered as a promising solution for the
above two limitations.
A. Occupancy Probability Contribution The following approximate expression is used for calculating
tunneling probability:-
Relation between the tunneling current and the Fermi–Dirac
distributions
1. Device:
2. Band Diagram: