Received 14 February 2025, accepted 3 April 2025, date of publication 7 April 2025, date of current version 18 April 2025.

Digital Object Identifier 10.1109/ACCESS.2025.3558617

1-ϕ Seven-Level Switched-Capacitor Boost

Multilevel Inverter Topology With
Optimized Number of Components
AHMED AWADELSEED , (Graduate Student Member, IEEE),
ARKADIUSZ LEWICKI , (Senior Member, IEEE),
AND DMYTRO KONDRATENKO
Faculty of Electrical and Control Engineering, Gdansk University of Technology, 80-233 Gdansk, Poland
Corresponding author: Ahmed Awadelseed ([email protected])
This work was supported by the National Science Centre, Poland, under Grant 2024/53/N/ST7/00711.

ABSTRACT Increasing the voltage of energy sources, such as photovoltaic (PV), fuel cells, and battery
storage units, requires a voltage-boosting technique. This paper introduces an efficient switched-capacitor
multilevel inverter (SC-MLI) capable of generating a boosted seven-level output voltage. The key advantages
of this topology include the inherent self-balancing of capacitor voltages without the need for auxiliary
balancing technique. Additionally, the proposed SC-MLI offers numerous features such as lower voltage
stress, improved efficiency, and reduced overall cost. The proposed topology has been evaluated based on
parameters such as component count, THD, cost, and efficiency. Experimental validation was conducted
on a 1.0 kW prototype setup under varying modulation index and sudden load changes. Finally, a thorough
comparison with state-of-the-art seven-level multilevel inverters highlighted the features of the proposed
topology.

INDEX TERMS Multilevel inverter, switched capacitor (SC), self-voltage balancing, boost capability.

I. INTRODUCTION To address these problems, Several efforts are being

The growing demand for high-quality power in various indus- undertaken to generate high voltage levels with fewer com-
tries has led to an increase in research on multilevel inverters ponents, lesser dc sources, self-voltage balancing properties,
(MLIs). These industries include motor drives, renewable and boosting capabilities [3], [4]. These topologies generate
energy, and electric vehicles. However, conventional MLIs higher voltage levels with fewer switches. However, asym-
such as Neutral Point Clamped diode (NPC), Flying Capac- metrical type of configuration increase the switching stress
itor (FC), and Cascaded H-Bridge (CHB) suffer from high on each switch. The authors in [5] used seven switches,
voltage stress, higher THD, and low efficiency. To over- two diodes, and two capacitors to generate 7-level wave-
come these issues, switched-capacitor multilevel inverters form with voltage gain of 1.5. Although the topology uses
(SC-MLIs) have been developed, offering several advantages a reduced number of switches, the diode cause significant
over conventional MLIs [1], [2]. SC-MLIs also offer reduced power loss. An SC-MLI with a single DC source and four
voltage stress and the rate of voltage change (dv/dt), which capacitors is described in [6]. Eight power switches and two
decreases power losses. However, SC-MLIs require more diodes are used to generate a 5, 7, 9 and 11-levels waveform.
power semiconductor devices and isolated SC sources, which Nevertheless, the large number of capacitors used in this
increases costs and reduces efficiency and reliability. topology increases the cost of the inverter. The topology
in [7] proposed a 7-level inverter with triple-voltage boost-
The associate editor coordinating the review of this manuscript and ing. To achieve this gain, the topology used three H-bridge
approving it for publication was Liu Hongchen . cells and three switched capacitors. Recently, a 7-level MLI
2025 The Authors. This work is licensed under a Creative Commons Attribution 4.0 License.
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 A. Awadelseed et al.: 1-ϕ Seven-Level Switched-Capacitor Boost Multilevel Inverter Topology

topology was developed by [8] using seven power switches devices with different ratings. More recently, an active-
and one capacitor to achieve an output voltage of 1.5 gain. neutral-point-clamped (ANPC) inverter based on a novel
However, the configuration utilizes seven diodes, which sig- single-stage boost inverter was investigated. In [26] and [27],
nificantly increases losses and reduces inverter efficiency. hybrid-ANPC was proposed to generating 7-levels with a
To minimize the voltage stress on the switches, many boost factor of 1.5. It appears that the number of switching
SC-MLI have been introduced [9], [10], [11], [12]. The capacitors and power semiconductor devices in each MLI
author in [9] described an improved configuration that gen- topology is constrained. However, they cannot provide an
erates seven levels using ten semiconductor switches and output voltage in an efficient manner. Another T-type NPC
two capacitors. The author was able to reduce the voltage topology is presented [28]. The topology implemented con-
stress by limiting switches blocking voltage to Vdc . Fur- trol technique to independently control the output voltage to
thermore, capacitors require a high capacitance. In [10] a supply single phase or three phase load. T-type topology with
7-level inverter was configured with ten switches, a single minimized voltage stress is presented in [29]. the proposed
DC voltage source, and three capacitors. It can be scaled for topology is also superior in its flexible extensibility and capa-
higher voltage gain by incorporating four additional switches bility of supplying inductive loads.
and exhibits features such as self-voltage balancing, parallel This study introduces an innovative seven-level SCMLI
capacitor operation, reduced voltage stress on the switches, topology with the following attributes to address the afore-
and inherent polarity reversal. The authors in [11] improved mentioned challenges.
the efficiency of the inverter and reduced the stress on power • Reduced number of components.
devices using an inductor to provide soft charging to the • Boosting Ability (Vo = 3 × Vin).
capacitor. In [12], a common ground SC-MLI was proposed, • Self-balancing of capacitors.
which utilizes nine switches, one diode, and two capacitors to • Bidirectional power flow capability.
achieve seven levels. The topology presented in [13] is able • Minimized voltage stress.
to generate higher number of voltage levels with fault tolerant As shown in Fig. 1, the inherent characteristics of the pro-
capability. However, the topology requires higher number of posed topology make it possible to apply it to a variety of
components. systems, such as fuel cells, battery-powered systems, Solar
To reduce the dc source and switched-capacitor current Photovoltaic (PV) arrays, and industrial motors. Furthermore,
spikes, an inductor is incorporated into the capacitor charging the recommended topology is ideally suited for implemen-
loop [14], [15]. The topology in [14] employs 12 power tation in microgrids, which supply electricity to isolated
switches and two capacitors to achieve a triple voltage boost areas.
gain, while the topology in [15] utilizes 10 switches and a
single capacitor to produce a 7-level output voltage with a
voltage gain of 3.0. However, the inclusion of an inductor
increases the inverter size and decreases its efficiency.
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SC-MLI for grid-connected PV systems was presented

in [16], [17], and [18]. Nevertheless, the boosting factor
is not sufficiently high compared with other MLI struc-
tures that utilize three SC units. This drawback results in
reduced reliability, escalated switch capacity requirements,
and increased costs of the proposed inverter structure. The
topologies discussed in [19], [20], [11], and [21] have triple-
boosting capability, but at the same time, they require a FIGURE 1. The block diagram of the proposed SC-MLI is used to interface
large number of components. The compact inverter presented various sources and loads.
in [22] achieved a reduction in switches for 7-level out-
put with double-boosting gain. This structure required an
H-bridge module to generate negative voltage levels.
A packed U cell topology is presented in [23]. The topology
successfully generates 7 levels using 6 power switches and
single switched capacitor fed from single dc source. Never-
theless, due to its lower voltage gain, the topology requires
multiple stages of power conversion for implementation with
renewable energy.
T-Type SC-MLI was investigated in [24] and [25]. How-
ever, the structure uses two different voltage ratings of dc-link
capacitors and switched capacitor voltages, which are not
recommended in the industry to select power semiconductor FIGURE 2. Proposed 7-level SC-MLI.

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II. PROPOSED SC-MLI TOPOLOGY TABLE 1. Switching state of the proposed SC-MLI inverter.
A. BRIEF DESCRIPTION OF THE BASIC SC-MLI UNIT
The suggested switching capacitor-based 7-level inverter
structure to provide a single AC output voltage is shown in
Fig. 2. With a voltage gain of 3.0, this setup creates 7 levels
using a single input source (Vdc ), 7 semiconductor switches
(S1 − S5 , S7 , and S8 ) with antiparallel diodes, one switch
(S6 ) without antiparallel diode, and 2 switching capacitors
(CSC1 –CSC2 ). To create an output voltage with 7 levels of
alternating current, the switching capacitors CSC1 and CSC2
are alternately charged by the input voltage supply Vdc and
discharged to the load. Each capacitor experiences a voltage
across it of 1.0Vdc , where Vdc is the magnitude of the input
voltage. Capacitor CSC1 is charged to 1.0Vdc through the
activation of switches S5 , S6 , and D whereas capacitor CSC2 C. BLOCKING VOLTAGE ON POWER SWITCHES
is similarly charged to 1.0Vdc by engaging switches S3 , S4 , The voltage rating of the switches is a vital factor in deciding
and S6 . the overall cost of the inverter, since it directly influences
In Fig. 3, red lines show the direction of current flow during the selection and sizing of switching components. The high-
various switching stages. In addition, a green illustration est voltage that a switch must block in order to function
shows how the switched capacitors charge. The voltage levels determines its voltage rating. Total Standing Voltage (TSV),
that the inverter can produce are 0Vdc , ±1.0Vdc , ±2.0Vdc , a crucial indicator for assessing the effectiveness and econ-
and ±3.0Vdc . Eight different switching layouts, which cor- omy of the inverter design, measures this total blocking
respond to the various operational modes of the proposed capacity across all switches. The maximum blocking voltages
inverter, are required to achieve these voltage levels. Fig. 3 for individual switches are stated in the proposed 7-level
shows the switching states for positive and negative voltage SC-MLI, which shows the hierarchical voltage distribution
generation, explaining the steps required to reach the desired throughout the system.
voltage levels.
VS1 = VS2 = VS7 = VS8 = 3.0Vdc (1)
B. DESCRIPTION OF OUTPUT VOLTAGE STATES VS6 = 2.0 Vdc (2)
Fig. 3(a-h) illustrate the output voltage levels produced by the VS3 = VS4 = VS5 = VD = 1.0Vdc (3)
suggested topology during the positive and negative cycles.
They are explained as follows: where, VS1 , VS2 , VS3 , VS4 , VS5 , VS6 , VS7 , VS8 , and D are the
maximum voltage stress across the switches S1 , S2 , S3 , S4 , S5 ,
State A (V o = 0): In this state, only four switches are
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• S6 , S7 , S8 ,and diode D. Therefore, TSV of the topology will

activated to produce a zero voltage level, as shown in be,
Fig. 3(d) and (a). During this state, capacitors CSC1 and
CSC1 begins to charge. TSV = 4 × 3.0 Vdc + 1 × 2.0 Vdc + 4 × 1.0V dc = 18.0 Vdc
• State B (V o = 1.0V dc ): As depicted in Fig. 3(b), (4)
capacitors CSC1 and CSC2 continue charging, resulting As the peak output voltage is 3.0Vdc, hence
in an output voltage of 1.0Vdc .
• State C(V o = 2.0V dc ): Illustrated in Fig. 3(c), this 18Vdc
TSV pu = = 6.0 (5)
state involves a configuration where capacitor CSC1 con- 3.0Vdc
tinue charging while capacitor CSC2 start discharging to Fig. 4 depicts the voltage stress distribution on various
form 2.0Vdc level. The current flows through switches switches.
S1 , S 5 , and S8 . Simultaneously, S6 turned on to charge
the switched capacitor CSC1 . D. CONTROL STRATEGY
• Sate D(V o = 3.0V dc ): Achieved by following the Single-carrier sinusoidal pulse width modulation
current path through switches S1 ,S 4 , S5 and S8 , as shown (SC-SPWM) is used to reduce the computational complex-
in Fig. 3(d). Both of capacitor CSC1 & CSC2 starts dis- ity associated with multi-carrier modulation methods and
charging. The output voltage level in this state is 3.0Vdc . avoid the requirement for synchronization between numerous
Analyses comparable to this can be conducted for the triangle signals. The final pulses achieved by comparing a
output voltage negative half cycle. As seen in Fig. 3, the green single triangular carrier signal with a sinusoidal modulating
color represents the charging action of the capacitors, while signal. The fundamental idea behind the suggested switching
the red color indicates the direction of current flow during technique is to compare the triangle carrier signal at the
various switching states. The 7-level output voltage generated intended switching frequency with the reshaped reference
by the switching pattern shown in Table 1. signal, which has been sinusoidally corrected to fit inside

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FIGURE 3. Positive voltage states of the proposed 7-level SC-MLI.

the single triangular carrier range. The modulating signal, the triangular carrier has a peak amplitude of (Atri ). Fig. 5
following reshaping, has an amplitude of (Aref ), whereas illustrates the evolution of the comparison zone on both the

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of required capacitance and natural voltage balance easier to

understand. As illustrated in Fig. 5,
This method of analyzing the operation during the positive
half-cycle proposed by author [30]. Understanding the impli-
cations on capacitance requirements and capacitor voltage
balance is much easier with this method.
1) Area (A): Voltage levels 0 and 1.0Vdc are fluctuate
during operations in Area-A. The rectified reference
signal (Aref ) is almost linear throughout each carrier
period (TS ) due to the high carrier frequency. This
makes it possible to compute duty cycle (δ) for levels
FIGURE 4. Voltage stress distribution of various switches. 1.0 and 0 in area-A more simply, as shown by equation:
(
δ1.0 = δθ = sin θ
(7)
positive and negative sides of the sinusoidal reference. The δ0 = 1 − δθ = 1 − sin θ
modulation index Ma is mathematically defined as The voltage (Vdc ) will shape the level 1.0Vdc . The following
Aref formula can be used to find the total charge in area-A (QA )
Ma = (6) that was applied to the load with a value of (ZL )
Atri
Z θ1
1
QA = io d(ωt)
ω
0
Z θ1 
1 Vdc
= 0 · (1 − δ(θ)) + δ(θ ) d(ωt)
ω ZL
0
Z θ1 
1 Vdc
= 0 · (1 − sin(θ)) + sin(θ) d(ωt) (8)
ω ZL
0
FIGURE 5. Modulation scheme. where ZL represents the output load. θ1 is the switching angle
of area-A as shown in Fig. 6.
2) Area (B): In this region, the output voltage alternates
between 1.0Vdc and 2.0Vdc . The corresponding duty
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cycles during the carrier period TS are mathematically

defined:
(
δ2.0 = δθ = sin θ
(9)
δ1.0 = 1 − δθ = 1 − sin θ
Here, level 1.0 Vdc is equal Vdc . Where, level 2.0Vdc is the
same as (Vdc − V CSC1 ) voltage. Therefore, QB supplied to the
load can be obtained as:
Z θ2
1
FIGURE 6. PWM expansion for different areas. QB = io d(ωt)
ω
θ1

E. SIZING OF THE CAPACITORS Z θ2 

1 Vdc − VCSC2 Vdc
In switched capacitor-based inverters, choosing the proper = (1 − δ(θ)) + δ(θ ) d(ωt)
ω ZL ZL
switched capacitors (SC) is essential for reducing voltage rip- θ1
ple, which has an impact on the output voltage’s quality. The Z θ2 
performance of the inverter is enhanced by appropriate SC 1 Vdc − VCSC1 Vdc
= (1 − sin(θ)) + sin(θ) d(ωt)
selection, which reduces ripple and harmonic distortion [23]. ω ZL ZL
θ1
During the voltage levels ±3.0Vdc and ±2.0Vdc , the float-
(10)
ing capacitors (CSC1 - CSC2 ) discharges. These two voltage
levels are symmetrical during the positive and negative half- 3) Area (C): The output voltage in Area (C) alternates
cycle. The modulation index Ma is set to 1.0 to make the study between 2.0Vdc and 3.0Vdc . To determine how long

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each voltage level is applied, the corresponding duty At the steady state of capacitors the average current should
cycles for these levels during the carrier time are be 0. Hence, we can achieve VCSC1 = VCSC2 = 1.0Vdc .
computed: Therefore, The voltage across the switched capacitor will
( be naturally balanced without the need of external circuit.
δ3.0 = δθ = sin θ The gate pulses necessary for the proposed 7-level SC-MLI
(11)
δ2.0 = 1 − δθ = 1 − sin θ switching operation have been generated to perform all three
In this region, voltage level 3.0Vdc is equal to (Vdc + V CSC1 ), functions (active power, reactive power, and capacitor charg-
and voltage level 2.0Vdc is equal to Vdc + V CSC1 + VCSC2 .. ing) as illustrated in Fig. 7.
Hence, the total charge (QC ) can be determined by:
Z θ3
1
QC = io d(ωt)
ω
θ2
Z θ3
1 Vdc + VCSC1
= (1 − δ(θ ))
ω ZL
θ2

Vdc + VCSC1 + VCSC2
+ δ(θ ) d(ωt)
ZL
Z θ3
1 Vdc + VCSC1
= (1 − sin(θ))
ω ZL
θ2

Vdc + VCSC1 + VCSC2
+ sin(θ) d(ωt) FIGURE 7. Gate pulses of the power switches S1 - S7 (a-g) of
ZL
theproposed 7-level SC-MLI.
(12)
The total charge in the negative half-cycle is similarly
characterized due to the symmetric operation of (CSC1 - CSC2 )
and can be calculated as: III. COMPARATIVE ANALYSIS WITH CONTEMPORARY
SEVEN-LEVEL INVERTERS
Z θ1 
In this section, the practicality of the presented SC-MLI is
1 Vdc
Q−A = 0 · (1 − sin(θ)) + sin(θ) d(ωt) (13) validated by comparing the number (NSW ), number of drivers
ω ZL
0 (NGD ), number of capacitors (NC ), per unit value of voltage
Z θ2
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 stress (TSVp.u ), and the total efficiency (η). Table 2 presents a

1 Vdc −VCSC2 Vdc
Q−B = (1−sin(θ))+ sin(θ) d(ωt) detailed comparison of these topologies based on the selected
ω ZL ZL criteria.
θ1
(14) The proposed topologies in [10], [16], [24], [25], and [26],
Z θ3 capable of generating 7 output voltage levels. Nevertheless,
1 Vdc + VCSC2 these topologies require high number of components. The
Q−C = (1 − sin(θ))
ω ZL voltage ratings of these components are more and it offer
θ2 lower voltage gain which considered high cost topologies.

Vdc + VCSC1 + VCSC2 The authors in [20] and [22] proposed high gain configu-
+ sin(θ) d(ωt) (15)
ZL ration. However these topologies suffer from high voltage
The average current (iavg ) passing through the neutral point stress on power switches which increases the losses and [20]
over one fundamental cycle can be derived from equa- requires a backend H-bridge and two dc sources.
tions (8), (10), (12), (13), (14), and (15), reflecting the net In terms of reliability, the capacitors are an important
current contributions from various operational states as: parameter and the proposed 7-L topology has a fewer num-
ber of capacitors than that in [10]. Although the topology
iavg
presented in [19] requires only two capacitors, it has a large
D
2X number of switches with four additional diodes. In addition,
= (Qx − Qy ) = 0 the proposed topology has significantly lower TSV p.u.,
T
i=A
However, [12] and [19] has low TSV p.u. but it faces the
(4 + 2π − θ1 − 3θ3 ) − 4(cos θ1 + cosθ 3 )
 
2  problem of high number of components.
⇒ −(VCSC1 − VCSC2 )(4+2π −2θ1 +4θ2 −6θ3 = 0 Cost and conducting device analysis of the proposed
ωTZL +8(cos θ − cos θ + cos θ ))
1 2 3 7-L topology has been studied in more details. By taking into
Qx ≡ QA , QB , and QC ; Qy ≡ Q−A , Q−B , and Q−C account the number of devices and their voltage ratings, the

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cost factor (CF) of the topologies can be calculated [11].

(NIS + NSW + Nd + Nc + Ngd + TSVpu )
CF = (16)
NL
The CF of the topologies is presented in Table 2. It can
be observed that the topologies in [10], [12], [17], [18],
[19], [20], [22], [24], and [25] have higher costs due to their
requirement for a higher component count. The topology
presented in [23] has a lower cost compared to the proposed
topology. However, it has lower voltage gain and efficiency
compared to the proposed topology.
The efficiency has been estimated using PLECS software
and the thermal modelling of the proposed topology. The con-
tribution of the components such as power switches, diode,
and SCs in the power loss has been given in Fig. 8(a). Fig. 8(b)
shows the fluctuation of the suggested topology efficiency in
relation to the load placed on the inverter. It can be observed
that when the load demand on the proposed 7-level SC-MLI
increases, the inverter efficiency falls. However, at 1.0 kW,
the proposed topology achieved 95.3%.
The proposed topology has a lower value of CF than the
majority of the topologies shown in Table 2. An efficient
and cost-effective power electronics circuit’s design greatly
depends on a thorough understanding of its power loss. The
associated conduction losses, switching losses, and losses in
capacitors are the four significant losses that are taken into
account while performing a loss analysis of a power circuit. FIGURE 8. Power Loss analysis of the invented topology with
The total power losses calculated using PLECS software. Infi- (a) powerloss distribution and (b) efficiency plot.
neon IKW25N120H3 IGBT power switches used to estimate
these losses. The average total conducting device average in
the proposed topology are less than that of topologies of [19]
and [24]. Table 2 presents the efficiency comparison, showing
that the suggested 7-L outperforms all other topologies.
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IV. RESULTS AND DISCUSSION

This section analyzes and discusses the simulation and
experimental results of the proposed quadruple-boost 7-level
inverter.

A. SIMULATION RESULTS
To assess the performance of the proposed MLI architecture,
a variety of static and dynamic scenarios have been simulated.
To evaluate the performance of the proposed MLI architec-
ture, The topology was tested under various load conditions
including changing load type, changing modulation index,
and when there is sudden change in load parameters. The sim- FIGURE 9. Simulation results under steady state condition.
ulation results were obtained using PLECS software. A 100V
source was used to assess the inverter’s performance.
The load voltage, load current, and capacitor voltages result. Another dynamic circumstance that is taken into con-
(VCSC1 , VCSC2 ) are shown in Fig. 9 under steady state. It can be sideration is a change in the modulation index (Ma ), which
observed that the capacitors remain balanced and achieving comes after the scenarios where the load undergo change.
7-levels at output voltage. This scenario is illustrated in Fig. 11. At Ma = 1.0. It can
Additionally, a dynamic condition test is performed on the be observed that, the output voltage levels are generated with
topology when sudden change on load from (20+40mH) to full control over capacitor voltage. Also, it is noticed that
(10+20mH) as depicted in Fig. 10. The sinusoidal current even after Ma was to 0.5 and then 0.2, the recommended
waveform that followed the load change instant is seen in this topology continued to work effectively with fewer levels.

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TABLE 2. Comparison table for different MLI-Topologies with proposed topology.

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FIGURE 11. Simulation results under modulation index change.

FIGURE 10. Simulation results under load change.

These results show that the proposed circuit can work in a

range of operational conditions.

B. EXPERIMENTAL RESULTS
A laboratory prototype with a power rating of 1.0kW is
prepared in order to confirm the performance of proposed
topology. Experimental results are recorded under various
load scenarios. The experimental configuration of the pro-
posed inverter is shown in Fig. 12. In order to generate gate
pulses for power semiconductor switches, SC-PWM is imple- FIGURE 12. Prototype setup.
mented and TMS320F28379D microcontroller is used to fire
power switches. The specification of experimental setup is As shown in Fig. 13(a) & (b), the maximum magnitude
shown in Table 3. of the output voltage is 300V with a voltage step of 50V

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TABLE 3. Parameters of experimental setup.

FIGURE 14. Experimental results under modulation index variations.

FIGURE 13. Experimental results (a) 7 level output voltage (b) RL load.
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when the voltage supply of input magnitude is 100V. The

waveforms of the switched capacitors voltage, output voltage,
and load current with a (30 + 60mH) load are displayed in
Fig. 13 (a) & (b).
The prototype configuration is prepared to validate the
proposed topology under load fluctuation from R=30,
L=60mH to R=15, L=30mH and from R=15, L=30mH
to R=30, L=60mH. The associated waveforms are dis-
played in Fig. 14(a) & (b). It demonstrates that under
conditions of sudden load changes, the proposed topology
can maintain the SC voltages and output voltage levels. Fur-
thermore, the variation of the modulation from 1.0 to 0.5 and
from 1.0 to 0.2 is implemented in the experimental setup
and corresponding results are shown in Fig. 15 (a) & (b) FIGURE 15. Experimental results of modulation index variations:
confirming the satisfactory dynamic performance. It can be a) fromMa=1.0 to 0.5, and b) from Ma=1.0 to 0.2.
seen that the proposed topology is able to offer a voltage gain
of 3.0 when Ma fluctuates between (1.0 and 0.7). However,
when Ma is between (0.7 and 0.3), the voltage gain drops to even under a low modulation index. This capability ensures
(VO = 2.0Vdc ). Finally, if Ma drops below 0.3, the inverter reliable operation during a wide range of modulation indices.
generates two levels at unity gain. The main feature of this Another test is conducted to verify the performance of the
topology is that the inverter continues supplying the load proposed topology for various load types. A sudden load

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FIGURE 16. Experimental results with load type change.

FIGURE 17. Waveforms of SC Voltage, ac components, and current.

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FIGURE 19. Experimental results of switches current and voltage.

FIGURE 18. Experimental results under input voltage variations. FIGURE 20. Harmonic profile of output voltage at 50Hz.

change from (30 + 60mH) to a purely resistive load of capacitor voltage balance under this condition, as shown in
(30). Its observed that, the inverter effectively maintains Fig.16.

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In order to show the self-balance of both switched capac- [6] M. A. E. Al-Hitmi, A. Iqbal, S. Islam, M. R. Hussan, and A. Abbas, ‘‘A
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AHMED AWADELSEED (Graduate Student

Member, IEEE) received the B.Sc. degree in
electrical engineering from Kordofan University, DMYTRO KONDRATENKO received the M.S.
Sudan, and the M.Sc. degree in power electronics degree from the National Technical Univer-
and drives from the National Institute of Tech- sity of Ukraine ‘‘Igor Sikorsky Kyiv Polytech-
nology (NIT) Warangal, India. He is currently nic Institute,’’ Kyiv, Ukraine, in 2018, and the
pursuing the Ph.D. degree with the Department M.S. and Ph.D. degrees in electrical engineering
of Automatic Control of Electric Drives, Gdansk from Gdansk University of Technology, Gdansk,
University of Technology. He was a Research Poland, in 2019 and 2024, respectively. His
Assistant with the Department of Electrical Engi- research interests include concentrated on pulse-
neering, Qatar University, Doha, Qatar. His research interests include step-up width modulation techniques, multilevel inverters,
power electronics converters (dc/ac and dc/dc), multilevel inverter topolo- multiphase and multi-motor drive systems, and
gies, and their control. He is serving as a regular reviewer for various journals sensorless control of electrical machines.
of IEEE, Wiley, and IET.
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