[Problem 1] [18pts]

A circuit has three inputs RST and four outputs UVWY. RST represents a binary coded-decimal digit. UV
represents the quotient and WY the remainder when RST is divided by 3 (UV and WY represent 2-bit and
2-bit binary numbers).
(a) Construct a ROM table [4pts]

[Figure 1]
Solution:

R S T U V W Y
0 0 0 0 0 0 0
0 0 1 0 0 0 1
0 1 0 0 0 1 0
0 1 1 0 1 0 0
1 0 0 0 1 0 1
1 0 1 0 1 1 0
1 1 0 1 0 0 0
1 1 1 1 0 0 1
(b) Construct a minimum two-level NAND-gate circuit (you can also use inverters). [4pts]

Solution:

(c) Specify a PLA table and the connection diagram for the PLA. [10pts]

Solution:
Product Inputs Outputs
Term R S T U V W Y
RS 1 1 - 1 0 0 0
RS 1 0 - 0 1 0 0
RST 0 1 1 0 1 0 0
RST 1 0 1 0 0 1 0
RST 0 1 0 0 0 1 0
RST 1 0 0 0 0 0 1
RST 0 0 1 0 0 0 1
RST 1 1 1 0 0 0 1
PLA table (point 5)
PLA connection (point 5)

[Problem 2] [22pts]

(a) Construct a D flip-flop using an inverter and an S-R flip-flop. [4pts]

Solution:

When D=0, then S=0, and R=1, so Q+ = 0

When D=1, then S=1, and R=0, so Q+ = 1

(b) If the propagation delay and setup time of the S-R flip-flop in (a) are 2.5ns and 1.5ns, respectively, and
if the inverter has a propagation delay of 1ns, what are the propagation delay and setup time of the D
flip-flop of part (a)? [6pts]

Solution:

R will not be ready until D goes through the inverter, so we must add the delay of the inverter to the setup time:
Setup Time = 1.5 + 1 = 2.5 ns
Propagation delay of the DFF: 2.5 ns (same as for the S-R flip-flop, since the propagation delay is measured
with respect to the clock)

Setup time (point 3)

Propagation delay (point 3)
(c) Design a 3-bit counter which counts in the sequence:
000, 001, 011, 010, 110, 111, 101, 100, (repeat) 000… by using the D flip-flop constructed in (a) as simple as
possible. (Use only two input NAND gates in addition to the D flip-flops) [7pts]

Solution:

Present State Next State

C B A C+ B+ A+
0 0 0 0 0 1
0 0 1 0 1 1
0 1 1 0 1 0
0 1 0 1 1 0
1 1 0 1 1 1
1 1 1 1 0 1
1 0 1 1 0 0
1 0 0 0 0 0

C+ = CA+BA’
B+ = C’A+BA’
A+ = C’B’+CB
Table/Kmap (point 4)
3-bit counter (point 3)

(d) What is the maximum clock speed of this circuit? Use the propagation delay and setup time extracted
from (b). The propagation delay of each logic gate is 1ns. [5pts]

Solution:

2.5 1 3 2.5
1
125MHz
8
[Problem 3][20pts]
Construct a "divisible-by-3" circuit that accepts a binary number entered one bit at a time, most
significant bit first, and indicates with a light if the number entered so far is divisible by 3. (The output of
“1” turns on the light.)

(a) Draw a Moore state graph for the circuit indicating the initial state. (Hint: the machine has 3 states.)
[15pts]

Solution:
If the value of the number entered so far is N, then after the digit b is entered, the value of the new number N' is
2N + b. Using this fact:

if N is 0 mod 3 then for some p, N = 3p + 0. After the digit b is entered, N' = 6p + b. So N' is b mod 3.
if N is 1 mod 3 then for some p, N = 3p + 1. After the digit b is entered, N' = 6p + 2 + b. So N' is b+2 mod 3.
if N is 2 mod 3 then for some p, N = 3p + 2. After the digit b is entered, N' = 6p + 4 + b. So N' is b+1 mod 3.

This leads to the following transition diagram where the state numbers represent the value of N mod 3.

(b) Construct a state table. [5pts]

Solution:

Next State
Present State Present Output (Light)
X=0 X=1
S0 S0 S1 1

S1 S2 S0 0

S2 S1 S2 0
[Problem 4] [20pts]
For the following state table:

Present Present
Next State
State Output
X=0 1 Z
A A B 1
B C E 0
C F G 1
D C A 0
E I G 1
F H I 1
G C F 0
H F B 1
I C E 0

(a) Reduce the state table to a minimum number of states using implication charts. [10pts]

Solution:

A≡F≡H, B≡I, D≡G

X=0 1 Z
A A B 1
B C E 0
C A D 1
D C A 0
E B D 1

Correct implication charts : 5pts

Correct reduced state table : 5 pts
(b) Use the guideline method to determine a suitable assignment for the reduced table. [5pts]

Solution:

Guideline 1 : (A,C) √ (B,D) √ (C,E) √

Guideline2 : (A,B) √ (C,E) √ (A,D) (A,C) √ (B,D) √
Guideline3 : (A,C,E) √ (B,D) √

ⓐA=000, B=100, C=001, D=101, E=011

ⓑA=000, B=010, C=001, D=110, E=011

Correct guideline : 3 pts

Suitable assignment : 2 pts

(c) Implement the table using D flip-flop. [5pts]

Solution:

ⓐ : A=000, B=100, C=001, D=101, E=011

Q1+Q2+Q3+
Q1Q2Q3 X=0 X=1 Z
000 000 100 1
100 001 011 0
001 000 101 1
101 001 000 0
011 100 101 1
 XQ1 XQ1
Q2Q3 00 01 11 10 Q2Q3 00 01 11 10
00 0 0 0 1 00 0 0 1 0

01 0 0 0 1 01 0 0 0 0

11 1 X X 1 11 0 X X 0

10 X X X X 10 X X X X

XQ1 Q1
Q2Q3 00 01 11 10 Q2Q3 0 1
00 0 1 1 0 00 1 0
01 0 1 0 1 01 1 0
11 0 X X 1 11 1 X
10 X X X X 10 X X
Q1+ = XQ1’+Q2 , Q2+ = XQ1Q3’ , Q3+ = X’Q1+XQ1’Q3+Q1Q3’ , Z = Q1’
ⓑ : A=000, B=010, C=001, D=110, E=011
Q1+Q2+Q3+
Q1Q2Q3 X=0 X=1 Z
000 000 010 1
010 001 011 0
001 000 110 1
110 001 000 0
011 010 110 1
 XQ1 XQ1
Q2Q3 00 01 11 10 Q2Q3 00 01 11 10
00 0 X X 0 00 0 X X 1

01 0 X X 1 01 0 X X 1

11 0 X X 1 11 1 X X 1

10 0 0 0 0 10 0 0 0 1

XQ1 Q1
Q2Q3 00 01 11 10 Q2Q3 0 1
00 0 X X 0 00 1 X
01 0 X X 0 01 1 X
11 0 X X 0 11 1 X
10 1 1 0 1 10 0 0
Q1+ = XQ3 , Q2+ = Q2Q3+XQ1’ , Q3+ = X’Q1+Q1’Q2Q3’ , Z = Q2’+Q3

Each error : -1 point

[Problem 5] [20pts]

Design a circuit which sets a specified number of bits on the right side of a shift register to 0. The number of bits
to be set to 0 is in register N before the start of the operation. When St = 1, the control block should shift right N
times, and then shift left N times. Assume St = 1 for one clock period at the start of the operation. The counter
only counts down, and K = 1 when the counter reaches 000. Note that the counter does not count up, so you will
have to load N into the counter twice.

※ An example of the operation

The case : a specified number = 11011011, N = 100
After the operation, 11011011 is changed to 11010000

[Figure 2] is a block diagram for the system using these units:

1) a control block circuit
2) a 3-bit N register
3) a 3-bit down-counter with load input(Ld) and K output (which is 1 when the counter reaches 000)
4) an 8-bit right/left shift register which functions according to the table in [Figure 3]

[Figure 2] Block diagram

Inputs Next State Action

A B Q7+ Q6+ Q5+ Q4+ Q3+ Q2+ Q1+ Q0+
0 0 Q7+ Q6+ Q5+ Q4+ Q3+ Q2+ Q1+ Q0+ No change
0 1 SI Q7+ Q6+ Q5+ Q4+ Q3+ Q2+ Q1+ Right shift
1 0 Q6+ Q5+ Q4+ Q3+ Q2+ Q1+ Q0+ SI Left shift
1 1 D7+ D6+ D5+ D4+ D3+ D2+ D1+ D0+ Load a new data

[Figure 3] 8-bit right/left shift register

(a) Give the state graph for the control block circuit. Note that St = 1 for one clock period at the start of the
operation. [5 pts]

Solution:

or
(b) Complete the following table showing the operation of the circuit if the number of shift register is 10011101
and N = 011. (The initial value of the counter is 111 before the Ld signals.) [5 pts]

Solution:
Shift
Time State Counter Register St K A B Ld
t0 S0 111 10011101 0 0 0 0 0
t1 S0 111 10011101 1 0 0 0 1
t2 S1 011 10011101 0 0 0 1 0
t3 S1 010 01001110 0 0 0 1 0
t4 S1 001 00100111 0 0 0 1 0
t5 S1 000 00010011 0 1 0 0 1
t6 S2 011 00010011 0 0 1 0 0
t7 S2 010 00100110 0 0 1 0 0
t8 S2 001 01001100 0 0 1 0 0
t9 S2 000 10011000 0 1 0 0 0
t10 S0 000 10011000 0 1 0 0 0

(c) Implement the control block circuit using two D flip-flops. Use a straight binary assignment. [10 pts]
(Hint 1) Do not care the case of St = 1 after the operation starts, which means you can use don’t care term.
(Hint 2) Example of a straight binary assignment
If there exists 8 states, state assignment is like as follows: S0=000, S1=001, S2=010,…,S7=111

Solution:
[Problem 6] [25 pts]
Answer the following questions briefly.
(a) Do you want the set-up time short or long? Explain why. [5 pts]

Short set-up time is preferred. With the same propagation delay of combinational logic, the short set-up time
brings a small clock period by t p  t d max  t su  Tc , as a result, higher clock frequency is possible.

(b) Do you want the hold time short or long? Explain why. [5 pts]

Short hold time is preferred. Short hold time reduces the possibility of race. That is, t p  t d min  t h can be
easily met, so that additional delay elements are NOT necessary.

(c) What will you choose between parallel processing and serial processing if clock frequency is high enough
and space for hardware is limited? Why? [5 pts]

Serial processing will be chosen. Serial processing requires less hardware but multiple clock cycles to
execute an operation. Since space for hardware is limited, obviously serial processing is better, and even
multiple clock cycles will not be a problem due to high clock frequency.

(d) Moore machine usually requires more states compared to Mealy machine. Why? [5 pts]

In Moore machine, the outputs are only determined by the states. Therefore in Moore machine, we need
more states to distinguish different outputs corresponding to each state, in other words, in Moore machine it
becomes more difficult for states to be reused.

(e) For the edge triggered SR flip-flop shown below, Q should be low at t = t5 because S = R = 0, meaning that Q
should hold the previous Q which is low, but Q is high at t = t5. Why? [5 pts]

[Figure 3. SR flip-flop.]

[Figure 4. Timing diagram of SR flip-flop.]

In the edge triggered SR flip-flop shown in Figure 3, when clock becomes low, master latch samples S and
R, and when clock become high, slave latch transfers the output of master latch to the flip-flop output.
From Figure 4, when clock becomes low, at t=t4, S is high and R is low, therefore, master latch sets P high.
This P which is high will be transferred to Q through slave latch when clock becomes high, at t=t5.