MT7615 Data Sheet v0.33 NoProtect
MT7615 Data Sheet v0.33 NoProtect
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Single Chip
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Version: 0.33
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Revision Date Author Description
0.1 2014-12-23 YW Lin Initial draft
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0.2 2014-12-26 YW Lin
0.21 2015-01-02 Ben Lin Updated features and pin layout
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0.3 2015-08-18 CH Hung Update Performance & Current consumption
0.31 2015-08-21 CH Hung Update feature and pin layout
0.33 2015-10-29 CH Hung Update DVDD11 range to TBD
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Table of Contents
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Document Revision History ............................................................................................. 2
Table of Contents.............................................................................................................. 3
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1 System Overview ...................................................................................................... 5
1.1 General Descriptions ............................................................................................................ 5
1.2 Features ................................................................................................................................ 5
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1.3 Operation Systems Support .................................................................................................. 6
1.4 Block Diagram ...................................................................................................................... 6
2 Product Descriptions ............................................................................................... 7
2.1 Pin Layout ............................................................................................................................ 7
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2.2 PIN Description .................................................................................................................... 7
2.3 Strapping Option ................................................................................................................. 11
2.4 IO Control Option ............................................................................................................... 12
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2.5 Package Information .......................................................................................................... 13
2.6 Ordering Information ......................................................................................................... 14
2.7 TOP Marking Information .................................................................................................. 15
3 Electrical Characteristics ....................................................................................... 16
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Lists of Tables and Figures
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Table 2-1. Pin descriptions ...................................................................................................................... 7
Table 2-2. Strapping option .................................................................................................................. 11
Table 2-3. IO control option ................................................................................................................. 12
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Table 2-4. Ordering information ........................................................................................................... 14
Table 3-1. Absolute maximum ratings................................................................................................... 16
Table 3-2. Recommended operating range ........................................................................................... 16
Table 3-3. DC description ..................................................................................................................... 16
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Table 3-4. Thermal information .............................................................................................................17
Table 3-5. WLAN current consumption .................................................................................................17
Table 3-6. 2.4GHz RF receiver specifications ....................................................................................... 18
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Table 3-7. 2.4GHz RF transmitter specifications .................................................................................. 20
Table 3-8. 5GHz RF receiver specifications .......................................................................................... 20
Table 3-9. 5GHz RF transmitter specifications ..................................................................................... 22
Table 3-10. PMU electrical characteristics ............................................................................................ 23
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1 System Overview
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1.1 General Descriptions
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MT7615 is a highly integrated Wi-Fi single chip which supports 1733 Mbps PHY rate. It fully complies
with IEEE 802.11ac and IEEE 802.11 a/b/g/n standards, offering feature-rich wireless connectivity at
high standards, and delivering reliable, cost-effective throughput from an extended distance.
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Optimized RF architecture and baseband algorithms provide superb performance and low power
consumption. Intelligent MAC design deploys a high efficient offload engine and hardware data
processing accelerators which completely offloads Wi-Fi task of the host processor. MT7615 is
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designed to support standard based features in the areas of security, quality of service and
international regulations, giving end users the greatest performance any time and in any circumstance.
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MT7615 supports concurrent dual-band operation at 5GHz and 2.4GHz band (DBDC, Dual-Band-
Dual-Concurrent). It enables diversified applications that require one link at 2.4GHz band, and the
other at less crowded 5GHz band simultaneously.
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With the advent of 802.11ac, multiuser MIMO (MU-MIMO) is defined. MT7615 supports MU-MIMO
with different configurations. An AP is able to use its antenna arrays to transmit multiple frames to
different clients at the same time and over the same frequency spectrum.
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1.2 Features
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Proprietary LTE coexistence over UART
WoWLAN via GPIO (client mode), supports Host Sleep (AP mode)
Compact 12mm*12mm DRQFN118 package with PCIe Gen2 interface
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1.3 Operation Systems Support
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Linux
OpenWrt
Android
2 Product Descriptions
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2.1 Pin Layout
MT7615 uses a 118 pins DR-QFN package. The pin order is shown below.
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DRQFN Default
Pin name Pin description I/O Supply domain
118 PU/PD
DRQFN Default
Pin name Pin description I/O Supply domain
118 PU/PD
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Reset and clocks
56 LDO_RST_N External system reset active low PU Input DVDD33
5 XO Crystal input or external clock input N/A Input AVDD16_XO
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PCIe interface
Request system to wake from the
37 WAKE_N PU In/out DVDD33
sleep/suspend state
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38 CLK_REQ_N Reference clock request signal PD In/out DVDD33
55 PERST_N PCIe functional reset PU Input DVDD33
44 PCIE_CLKN PCIe differential reference clock N/A Input AVDD33_PCIE
45 PCIE_CLKP PCIe differential reference clock N/A Input AVDD33_PCIE
48
50
52
PCIE_TXN
PCIE_TXP
PCIE_RXN
PCIe transmit differential pair
PCIe transmit differential pair
PCIe receive differential pair
ID N/A
N/A
N/A
Output
Output
Input
AVDD33_PCIE
AVDD33_PCIE
AVDD33_PCIE
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54 PCIE_RXP PCIe receive differential pair N/A Input AVDD33_PCIE
46 PCIE_VRT PCIe resister reference N/A Analog
EEPROM/flash interface
28 GPIO8/EEFL_CS External chip select PD In/out DVDD33
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DRQFN Default
Pin name Pin description I/O Supply domain
118 PU/PD
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39 GPIO16 Programmable input/output PU In/out DVDD33
41 GPIO17 Programmable input/output PU In/out DVDD33
61 GPIO18 Programmable input/output PU In/out DVDD33
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62 GPIO19 Programmable input/output PU In/out DVDD33
64 GPIO20 Programmable input/output PU In/out DVDD33
66 GPIO21 Programmable input/output PD In/out DVDD33
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67 GPIO22 Programmable input/output PD In/out DVDD33
68 GPIO23 Programmable input/output PD In/out DVDD33
69 GPIO24 Programmable input/output PU In/out DVDD33
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71
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GPIO25
GPIO26
GPIO27
Programmable input/output
Programmable input/output
Programmable input/output
ID PU
PU
PU
In/out
In/out
In/out
DVDD33
DVDD33
DVDD33
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73 GPIO28 Programmable input/output PU In/out DVDD33
74 GPIO29 Programmable input/output PD In/out DVDD33
75 GPIO30 Programmable input/output PD In/out DVDD33
76 GPIO31 Programmable input/output PD In/out DVDD33
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DRQFN Default
Pin name Pin description I/O Supply domain
118 PU/PD
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118 WF0_RFION_G WF0 RF g-band RF port N/A In/Out
7 CLK_OUT_N XTAL buffered clock output N/A Output
8 CLK_OUT_P XTAL buffered clock output N/A Output
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PMU
43 CLDO LDO 1.15V output N/A Output
42 AVDD16_CLDO Digital LDO 1.68V power supply N/A Power
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40 AVDD33 3.3V power supply N/A Power
LTE coexistence
GPIO38/LTE_UART_
58 UART RX PU In/out DVDD33
RX
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GPIO39/LTE_UART_
TX
Power supplies
UART TX
ID PU In/out DVDD33
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18, 63 DVDD33 Digital 3.3v I/O power supply N/A Power
12, 25,
32,57,65
DVDD11 Digital 1.15v core power supply N/A Power
,77,78,7
9, 80
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DRQFN Default
Pin name Pin description I/O Supply domain
118 PU/PD
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6 NC Reserved N/A N/A
E-PAD VSS Ground N/A Ground
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2.3 Strapping Option
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Four pins are used to set up the default status of the chip for different normal mode applications. The
pins are all internally pulled down. Users can connect the pin with an external small resistor (1KΩ or
less) to VDD33 when they want to change the application. Those pins are sampled at Power-On-reset
to determine the default status.
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GPIO7 is used to identify if the external EEPROM or the internal Efuse is used. GPIO10 is used for
testing purpose, and the user should set up normal mode for normal application.
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Table 2-2. Strapping option
0: current mode
1: voltage mode Pull Down, 75K
co-clock mode Pull Down, 75K
GPIO8 (co-clock output High-Z ohm (PU/PD
selection ohm
buffer is default adjustable)
turned on)
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Note :
1) PAD pull-up/pull down setting when I/O 3.3V power is not ready.
2) PAD pull-up/pull down setting in strapping mode, i.e. power on reset is asserted or LDO_RST_N
is LOW.
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3) PAD pull-up/pull down setting in normal mode, i.e. power on reset is de-asserted and
LDO_RST_N is HIGH.
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MT7615 provides 41 configurable I/O functions to support diversified applications. The IO functions
can be configured through the control register PINMUX_SEL. It supports external front-end module
on dual bands for high power requirement. Open drained IOs are available for WLAN LED. The most
common configuration is listed in the table below.
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Table 2-3. IO control option
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MEDIATEK
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MT7615N : Part number
MT7615N DDDD : Date code
DDDD-#### #### : Internal control code
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BBBBBBB : Lot number
BBBBBBB
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Figure 2-4. Top marking
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3 Electrical Characteristics
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3.1 Absolute Maximum Rating
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Stresses beyond those conditions indicated in this section may cause permanent damage to the device.
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Symbol Parameters Max. rating Unit
AVDD33 3.3V supply voltage -0.3 to 3.63 V
DVDD33 3.3V supply voltage -0.3 to 3.63 V
AVDD16
DVDD11
TSTG
1.68V supply voltage
1.15V supply voltage
Storage temperature
ID -0.3 to 1.77
-0.3 to 1.265
-40 to +125
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V
°C
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VESD ESD protection (HBM) 2000 V
Functional operation beyond those conditions indicated in this section is not recommended.
3.3 DC Characteristics
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RPU Input pull-up resistance PU=high, PD=low 40 190 KΩ
RPD Input pull-down resistance PU=low, PD=high 40 190 KΩ
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3.4 Thermal Characteristics
Table 3-4. Thermal information
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Performance
Symbol Description
Typ. Unit
TJ Max. junction temperature (plastic package) 125 °C
ΘJA
ΘJC
ΨJt
Junction to ambient temperature thermal
Junction to case temperature thermal resistance
Junction to the package thermal resistance
ID resistance[1] 15.73
4.86
1.11
°C/W
°C/W
°C/W
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Note:
[1] JEDEC 4L 51-7 system FR4 PCB size: 76.2*114.3mm
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Performance
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Description
Typ. Unit
Sleep mode 5 mA
2.4GHz RX Active, HT40, MCS31 350 mA
5GHz RX Active, VHT80, MCS9, Nss=4 710 mA
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3.6.1 Wi-Fi RF Block Diagram
The frond-end loss with diplexer:
2.4GHz insertion loss is 1.5 dB 1
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5GHz insertion loss is 1.5 dB
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The specification in table below is defined at the antenna port, which includes the frond-end loss.
(Assume FE loss=1.5dB)
Performance
Parameter Description
Min. Typ. Max. Unit
Performance
Parameter Description
Min. Typ. Max. Unit
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Frequency range 2412 - 2484 MHz
1 Mbps CCK - -97 - dBm
2 Mbps CCK - -94 - dBm
RX sensitivity
5 Mbps CCK - -92 - dBm
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11 Mbps CCK - -89 - dBm
6 Mbps OFDM - -94 - dBm
9 Mbps OFDM - -91.5 - dBm
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12 Mbps OFDM - -91 - dBm
18 Mbps OFDM - -88.5 - dBm
RX sensitivity
24 Mbps OFDM - -85 - dBm
36 Mbps OFDM
48 Mbps OFDM
54 Mbps OFDM
MCS 0
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-82
-77.5
-76.5
-93.5
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dBm
dBm
dBm
dBm
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MCS 1 - -90 - dBm
MCS 2 - -87.5 - dBm
RX sensitivity
BW=20MHz MCS 3 - -84.5 - dBm
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Non-STBC
MCS 6 - -72.5 - dBm
MCS 7 - -71 - dBm
MCS 31 - -70.5 - dBm
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Performance
Parameter Description
Min. Typ. Max. Unit
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channel rejection
MCS 7 - Note* - dB
(HT20)
Receive adjacent MCS 0 - Note* - dB
channel rejection
MCS 7 - Note* - dB
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(HT40)
Note*: Receive adjacent channel rejection comply IEEE spec.
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3.6.3 Wi-Fi 2.4GHz Band RF Transmitter Specifications
The specification in table below is defined at the antenna port, which includes the frond-end loss.
(Assume FE loss=1.5dB)
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Table 3-7. 2.4GHz RF transmitter specifications
Performance
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Parameter Description
Min. Typ. Max. Unit
Frequency range 2412 - 2484 MHz
1~11 Mbps CCK - 21.5 - dBm
6 Mbps OFDM - 20.5 - dBm
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Note2: Second and third harmonic level correlate closely with diplexer’s rejection (Please refer to HDK for
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diplexer p/n)
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Performance
Parameter Description
Min. Typ. Max. Unit
Frequency range 5180 - 5825 GHz
RX sensitivity 6 Mbps OFDM - -93 - dBm
Performance
Parameter Description
Min. Typ. Max. Unit
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9 Mbps OFDM - -90.5 - dBm
12 Mbps OFDM - -90 - dBm
18 Mbps OFDM - -87.5 - dBm
24 Mbps OFDM - -84 - dBm
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36 Mbps OFDM - -81 - dBm
48 Mbps OFDM - -76.5 - dBm
54 Mbps OFDM - -75 - dBm
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MCS 0 - -92.5 - dBm
MCS 1 - -89 - dBm
MCS 2 - -86.5 - dBm
RX sensitivity
BW=20MHz VHT
Mixed Mode
800ns Guard Interval
Non-STBC
MCS 3
MCS 4
MCS 5
MCS 6
ID -
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-
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-83.5
-80
-75.5
-74.5
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-
-
dBm
dBm
dBm
dBm
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MCS 7 - -73 - dBm
MCS 8 - -68.5 - dBm
MCS 0 - -89 - dBm
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Mixed Mode
MCS 5 - -69.5 - dBm
800ns Guard Interval
Non-STBC MCS 6 - -68 - dBm
MCS 7 - -66.5 - dBm
MCS 8 - -62.5 - dBm
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Performance
Parameter Description
Min. Typ. Max. Unit
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MCS 5 - -66 - dBm
MCS 6 - -64.5 - dBm
MCS 7 - -63 - dBm
MCS 8 - -59 - dBm
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MCS 9 - -56.5 - dBm
6 Mbps OFDM - -10 - dBm
54 Mbps OFDM - -10 - dBm
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Maximum receive
level MCS0 - -10 - dBm
MCS7 - -10 - dBm
Receive adjacent MCS0 - Note* - dB
channel rejection
(VHT20)
Receive adjacent
channel rejection
MCS8
MCS 0 ID -
-
-
Note*
Note*
-
-
-
dB
dB
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(VHT40) MCS 7 Note* dB
(Assume FE loss=1.5dB)
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Performance
Parameter Description
Min. Typ. Max. Unit
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Note2: Second and third harmonic level correlate closely with diplexer’s rejection (Please refer to HDK for
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diplexer p/n)
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3.7 PMU Electrical Characteristics
Table 3-10. PMU electrical characteristics
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Performance
Parameter Conditions
Min. Typ. Max. Unit
PCIE LDO
Input voltage
Output voltage
Output current
ID 1.51
1.14
-
1.68
1.2
-
1.84
1.26
40
V
V
mA
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Quiescent current - 60 - uA
Note 1: The programmable range of the output voltage of the switching regulator is 0.8V to 2.3V.
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4 Functional Specification
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4.1 System
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4.1.1 Power Management Unit
Power Management Unit (PMU) contains Two Low Drop-out Regulators (LDOs), power-on reset and
the reference band-gap circuit. The circuits are optimized for quiescent current, drop-out voltage, and
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output noise.
Three power sources are required for MT7615, The 3.3V power source is directly supplied to EFuse
LDO, digital I/Os, PCIe PHY, and RF related circuit. The 1.68V power source is supplied to PCIe LDO
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and RF related circuit. The 1.15V power source is supplied to digital circuit.
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Vcc 3.3v
1.68V
MT7615
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PMIC
PMU
1.15V
3.3V EFuse LDO EFUSE
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Power Detector
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Power Detector
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4.1.2 EFUSE
MT7615 uses embedded Efuse to store device specific configuration information such as MAC
addresses, and power control settings.
MAC addresses
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NIC configuration: RF front-end configuration, LED mode, baseband configuration
Wi-Fi BeamForming parameter
PCIe PHY parameters
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It uses logical address mapping table scheme to make easy programming on efuse content.
The total efuse size is 7680 bits.
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4.1.3 GPIO
MT7615 has 41 GPIO pins with software access. Pins are multiplexed with other functions including
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the LED control, external RF front-end module control, LTE coexistence, etc. Each GPIO supports
internal pull-up/pull-down options as well as driving strength control.
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4.2 Host Interface Architecture
MT7615 supports the high-speed interface which conforms to the PCI Express Base Specification v2.0.
It supports PCIe link power states L0, L0s, L1, and L2. It also supports the new L1 sub-states to
provide low power modes of operation.
The interface contains all necessary function blocks including transaction layer, data link layer, and
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physical layer. The standard configuration space and extended configuration space are supported.
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R4 is a power efficient processor core with 8-stage dual issue pipeline and with tightly-coupled
memory system. It is based on ARMv7R architecture with Thumb-2 / ARM instruction set.
It allows Wi-Fi functions to be performed on MT7615 and minimizes the computing power required
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The radio MCU subsystem is used to perform Wi-Fi related functions. That includes the low power
function that can minimize the loading of CR4 and the host CPU.
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4.4 Wi-Fi Subsystem
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4.4.1 Wi-Fi MAC
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802.11 to 802.3 header translation offload
TCP/UDP/IP checksum offload
Multiple concurrent clients as an access point
Multiple concurrent clients as an repeater
Aggregates MPDU RX (de-aggregation) and TX (aggregation)
AMSDU in AMPDU support
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MU-MIMO supports four multi-user contains one primary user and three secondary users
DBDC supports 2.4G/5G active concurrently
Air time fairness and bandwidth control
Transmit rate adaptation
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processing
AES-CCMP and GCMP hardware processing
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steering matrix
Proprietary Implicit Beamforming
MU-MIMO configurations of
4 users: 4*1ss
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3 users: 1*1ss + 1*2ss or 3*1ss
2 users: 2*2ss or 1*1ss + 1*2ss or 2*1ss
DBDC
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Digital pre-distortion to enhance PA performance
Smoothing (channel estimation) extension to MIMO case
Dynamic frequency selection (DFS) radar pulse detection
Supports indoor location (802.11v)
packet-level transceiver concurrently.
ProprietaryrReceiver MIMO power save scheme.
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Proprietary dynamic channel bandwidth switching(DCBW) supports 160 2SS and 80 4SS
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4.4.3 WLAN RF
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ESD CAUTION
MT7615 is ESD (electrostatic discharge) sensitive device and may be damaged with ESD or spike
voltage. Although MT7615 is with built-in ESD protection circuitry, please handle with care to avoid
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the permanent malfunction or the performance degradation.
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