StartingwithSerial

Chapter10 Sections1,2,9,10

Dr.IyadJafar

Outline
Introduction SynchronousSerialCommunication AsynchronousSerialCommunication PhysicalLimitations OverviewofPIC16Series The16F87xAUSART Summary

Introduction
Microcontrollersneedtomovedatatoandfrom externaldevices Ingeneral,twoapproaches
Parallel
Datawordbitsaretransferredatthesametime Awireisdedicatedforeachbit Simpleandfastbutexpensive Shortdistances

Serial
Bitsaretransferredoneafteranotheroverthesamelink/wire Requirescomplexhardwaretotransmitandreceive Slow Shortandlongdistances

Introduction
Twomemoriesofthesamesize.However,one usesparalleltransferwhiletheotherusesserial

SerialCommunication
Bitsaretransferredoneafteranotheronthesame wire!!! Challenges
Howtodistinguishthestartandendofthebit? Howtodeterminethestartandendofaword?

Twoapproaches
Synchronousserialcommunication
Aseparateclocksignalissentinparallelwiththedata Eachclockcyclerepresentsonebitduration

Asynchronousserialcommunication
Noclocksignal! Timingisderivedfromthedataitself
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SerialCommunication

Synchronous

Asynchronous

SerialCommunication
Datainsidethememoryandmicroprocessorisformattedin parallel.Howtotransmititserially? Shiftregisters

SynchronousSerialCommunication

General Serial Link

Synchronous link implemented using a microcontroller

SynchronousSerialCommunication

Advantages Simple hardware Efficient High speed Disadvantages Extra line for the clock The bandwidth needed for the clock is twice the data bandwidth Data and clock may lose synchronization over long distance

AsynchronousSerialCommunication
Noclocksignal! Thetransmitterandreceivershouldoperatea clockatthesameratethatisintegermultipleof thedatarate(usually16) Tosynchronizetheclocksofthetransmitterand receiver,dataisframedwithastartandstopbits

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AsynchronousSerialCommunication
Framing

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AsynchronousSerialCommunication
Synchronization

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PhysicalLimitations
TimeConstanteffect

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PhysicalLimitations
TransmissionLineEffects
Characteristicimpedanceandreflections Linesshouldbeterminatedproperly

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PhysicalLimitations
ElectromagneticInterference

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PhysicalLimitations
GroundDifferentials

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OverviewofthePIC 16Series
Wehavealreadyseen thePIC16F84A Othermembersinthe serieshavemore features:
AdditionalI/Oports MoreHWtimers A/Dconverters LCDDrivers USARTs SynchronousSerial Comparators .

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OverviewofthePIC 16Series

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OverviewofthePIC16Series
InterruptLogicfor16F874A/16F877A

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OverviewofthePIC16Series
Device 16F873A 16F876A Pins 28 Features 3parallelports, 3counter/timers, 2capture/compare/PWM, 2serial, 510bitADC, 2comparators 5 parallelports, 3counter/timers, 2capture/compare/PWM, 2serial, 8 10bitADC, 2comparators

16F874A 16F877A

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The16F87xAUSART
The16F87XAfamilyhasaUniversalSynchronous AsynchronousReceiverTransmitter(USART)
Configurable Halfduplexsynchronousmasterorslave Fullduplexasynchronoustransmitterandreceiver

TheUSARTsharespinswithPORTC
pin7beingthereceiveline pin6beingthetransmitline

Operationinvolvesthefollowingregisters
TXSTA(0x98)TXREG(0x19)RCSTA(0x18) RCREG(0x1A)SPBRG(0x99)PIE1(0x8C) PIR1(0x0C)INTCON(0x0B,0x8B,0x10B,0x18B) TRISC(0x87)

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The16F87xAUSART
AsynchronousUSARTTransmitterBlockDiagram

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The16F87xAUSART
AsynchronousUSARTTransmitterOperationNotes
DataistransmittedLSB firstonRC6 pin TheshiftregisterTSR isbufferedbytheTXREG(19H)andisnot

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accessibleasamemorylocation TransmissioniscontrolledbytheTXEN bitwhichenablesthe clocktostartthetransmission ToenableserialtransmissiononRC6,bitSPEN inRCSTA register hastobeset Totransmitdata,itmustbeloadedintheTXREG.Itistransferred toTSR immediatelyifnotransmissionorafterthestopbitfrom previoustransmissionissentout Transmissionstatusisprovidedbytwobits: TXIFflaginPRR1registerindicatesthestatusofTXREG.Itis setwhendataistransferredtoTSR.Itisclearedonwritingto TXREG TRMTflaginTXSTAitissetwhentheshiftregisterisempty ParitybitcanbesentoutbyusingTXD9 bitand TX9inTXSTA

The16F87xAUSART
TXSTA(98H)

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The16F87xAUSART
StepsforUsingtheasynchronoustransmitter
1. 2. 3. 4. 5. 6. 7. 8.
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ClearTRISC<6>bittoconfigureRC6asoutput SettheSPBRG(0x99)registerandBRGH(TXSTA<2>)bittochoose theappropriatebaudrate EnableasynchronousserialportbyclearingtheSYNC(TXSTA<4>) bitandsettingtheSPENbit(RCTSA<7>) Ifinterruptsaredesired,settheTXIE(PIE1<4>),GIE(INTCON<7>), andPEIE (INTCON<6>) bits If9bittransmissionisdesired,settheTX9(TXSTA<6>)bit EnabletransmissionbysettingtheTXEN(TXSTA<5>),whichwill settheTXIF(PIR1<4>)bit If9bittransmissionisselected,thentheninthbitshouldbe loadedinTX9D(TXSTA<0>) LoaddatainTXREG(0x19)tostartthetransmission

The16F87xAUSART
Timingofasynchronoustransmission

Registersinvolvedinasynchronoustransmission

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The16F87xAUSART
AsynchronousReceiver

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The16F87xAUSART
AsynchronousUSARTReceiverOperationNotes
DataisreceivedLSB firstonRC7 pin ReceptionisenabledbytheCREN bit AttheheartoftheblockistheRSR register.Onceastopbitis

detected,dataistransferredtoRCREG register,ifitisempty,and theRCIFflagisset.OnreceiveinterruptcanbeenabledbyRCIE bit TheRCREG isFIFO doublebufferedregister

Itcanbereadtwicetoreadthereceivedtwobytes IfastopbitisdetectedinRSRandtheRCREGisstillfull,anoverrunerror occursandisindicatedinOERRbit(ThewordisRSRislost)

IfOERRbitisset,shiftingstopsinRSRandtransferstotheRCREGisinhibited!

Tocleartheframingerror,cleartheCRENbit.

IfthestopbitisreceivedasclearinRSR aframingerroroccursand

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isindicatedbytheFERR bit. The9th bitofdataRCD9 andFERR arealsodoublebuffered.Itis essentialtoreadtheRCSTA registerbeforetheRCREG toavoid losingthecorrespondingvaluesofRCD9 andFERR

The16F87xAUSART
RCSTA(18H)

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The16F87xAUSART
StepsforUsingtheasynchronousreceiver
1. 2. 3. 4. 5. 6. 7. 8. 9.
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SettheSPBEG(0x99)registerandBRGH(TXSTA<2>)bittochoose theappropriatebaudrate EnableasynchronousserialportbyclearingtheSYNC(TXSTA<4>) bitandsettingtheSPENbit(RCTSA<7>) Ifinterruptsaredesired,settheRCIE(PIE1<5>),GIE(INTCON<7>), andPEIE(INTCON<6>)bits If9bitreceptionisdesired,settheRX9(RCSTA<6>)bit EnablethereceptionbysettingbitCREN(RCSTA<4>) TheRCIF(PIR1<5>)willbesetwhenreceptionofonewordis completeandaninterruptwillbegeneratedifRCIEisset ReadtheRCSTA(0x18)togetthe9th bitanddetermineifany erroroccurred(OERR,FERR) Readthe8bitreceiveddatabyreadingRCREG(0x1A) Ifanyerroroccurred,cleartheerrorbyclearingtheCREN

The16F87xAUSART
Timingofasynchronousreception

Registersinvolvedinasynchronousreception

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The16F87xAUSART
TheBAUDRateGenerator
TheBAUDrateforUSARTiscontrolledbythevaluein theSPREG(99H),theSYNCand theBRGH bitsinthe TXSTA(19H)
SYNC BRGH=0 BRGH=1

0 (asynchronous)

Fosc 64( SPBRG + 1)

Fosc 16( SPBRG + 1)

1 (synchronous)

Fosc 4( SPBRG + 1)

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Example
Aprogramtotransmit3bytesstoredinlocations 0x40,0x41,and0x42seriallywithnoparityata rateof9.6Kbps.AssumePIC16F877Awith oscillatorfrequencyof20MHz Requirements 1.setuptheserialportfortransmission 2.choosetheappropriatevalueofSPBRGand BRGHtoproducetherequiredrate

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Example
#include org goto org goto org bsf bcf bcf movlw movwf bsf bcf bsf movlw mowf

Example
p16F877A.inc 0x0000 START 0x0004 ISR 0x0006 STATUS , RP0 STATUS , RP1 TRISC, 6 D31 SPBRG TXSTA, TXEN STATUS, RP0 RCSTA, SPEN 0x40 FSR ; include the definition file for 16F77A ; reset vector ; define the ISR ; Program starts here ; select bank 1 ; set RC6 as output ; set the SPBRG value ; select bank0 ; enable serial transmission ; FSR has the address of the first element

ISR START

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Example
TX movf movwf incf btfss goto movf sublw btfss goto goto end INDF, W TXREG FSR, F PIR1, TXIF WAIT FSR,W 0x43 STATUS, Z TX DONE ; read byte to transmit ; store in the transmission register ; increment FSR to point to next address ; check if the TXREG is empty

WAIT

; check if all values were transmitted

DONE

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Summary
Serialcommunicationtransmitsbitsoneafteranother intwomodes:synchronousandasynchronous Stableandaccurateclockingplaysanimportantrolein serialcommunication Itischeapertouseserialcommunicationoverlong distances Somemembersofthe16seriesareequippedwith synchronousandasynchronouscommunicationports Theseportscanbeconfiguredtooperatedindifferent modesandrates
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