Microprocessor and Embedded systems

Unit 1
8086 Processor: Architecture, Signals, Memory Organization, addressing modes, Instruction
Set, Assembler directives and operators, Assembly level programs for data processing,
searching, sorting, string manipulation and conversions, interrupts processing, 8087 Math-Co-
Processor

1.1 8086-HARDWARE ARCHITECTURE

The features of 8086 are:

 The 8086 is a 16-bit processor

 The 8086 has a 16-bit data bus

 The 8086 has a 20-bit address bus

 Direct addressing capability 1M byte of memory (220)

 It provides fourteen 16-bit register

 24 operand addressing modes

 Bit, byte, word and block operations.

 8 and 16 bit signed and unsigned arithmetic operations including multiply and divide

 Four general purpose 16 bit registers: AX, BX, CX, DX

 Two pointer group registers: stack pointer (SP), Base pointer(BP)

 Two index group registers: source index (SI), destination index (DI)

 Four segment registers: code segment (CS), Data segment (DS), Stack segment (SS),
Extra segment(ES)

 6 Status flag and 3 control flags.

 Memory is byte addressable- each address stores an 8-bit value.

 Address can be up to 32 bit long, resulting in 4GBof memory.

 Range of clock rates: 5MHZ for8086, 8MHZ for8086-2, 10MHZ for8086-1

 Multibus system compatible interface

 Available in 40 pin plastic package.

1.2 8086 Microprocessor Architecture:
The internal functions of 8086 processor are partitioned logically into two processing units.
The 8086 CPU is divided into two independent functional parts,
1. Bus Interface Unit (BIU)
2. Execution Unit (EU)
 The BIU and EU function independently.
 The BIU interface the 8086 to the outside world. The BIU fetches, reads data from
memory and ports, and writes data to memory and I/O ports.
 EU receives program instruction codes and data from the BIU, executes these instructions
and stores the results either in general registers or output them puts all its data through the
BIU.

The BIU contains

1. Segment Registers, 2. Instruction Pointer (IP), 3. Instruction Queue
The EU contains
1. ALU
2. General purpose registers
3. Index registers
4. Pointers
5. Flag register
 Figure: Architecture of 8086
General Purpose Registers All general registers of the 8086 microprocessor can be used for
arithmetic and logic operations. The 16-bit general purpose registers are
1. Accumulator register (AX)
2. Base register (BX)
3. Count register (CX)
4. Data register (DX)
(i) Accumulator register (AX)
 Accumulator (AX) is a 16-bit register; consists of two 8-bit registers AL and AH.
 AL contains the low-order byte of the word, and AH contains the higher order byte.
 Accumulator can be used for Input/ Output (I/O) operations and string manipulation.
(ii) Base register (BX)

 Base register (BX) is a 16-bit register; consist of two 8-bit registers BL and BH.
 BL consist the lower order byte of the word, and BH contains the higher order byte.
 BX register contains a data pointer used for based, based indexed or register indirect
addressing.

(iii) Count register (CX)

 Counter register (CX) is a 16-bit register; consists of two 8-bit registers CL and CH.

 CL register contain the low order byte of the word, and CH contains the high order byte.
 Count register can be used as a counter in string manipulation and shift/ rotate
instructions.

(iv)Data register (DX)

 Data register (DX) is a 16-bit register; consists of two 8-bit registers DL and DH.
 DL register contain the low order byte of the word, and DH contains the high order
byte.
 Data register can be used as a port number in I/O operations.
 In integer 32-bit multiply and divide instruction the DX register contains higher order
word of the initial or resulting number.
Segment Registers There are four different 64 KB segments for instructions, stack, data and
extra data. The segment registers are:
1. Code segment (CS)
2. Stack segment (SS)
3. Data segment (DS)
4. Extra segment (ES)

(i) Code segment (CS)

 Code segment is a 16-bit register containing address of 64 KB segment with processor

instructions.
 The processor uses CS register for all accesses to instructions referenced by instruction
pointer (IP).
 CS register cannot be changed directly.
 The CS register is automatically updated during FAR JUMP, FAR CALL and FAR
RET instructions
(ii) Stack segment (SS)

 Stack segment is a 16-bit register containing address of 64KB segment with program
stack.
 By default, the processor assumes that all data referenced by the stack pointer (SP) and
base pointer (BP) registers are located in the stack segment.
 SS register can be changed directly using POP instruction.

(iii) Data segment (DS)

 Data segment is a 16-bit register containing address of 64KB segment with program
data.
 By default, the processor assumes that all data referenced by general registers (AX, BX,
CX, and DX) and index register (SI, DI) is located in the data segment.
 DS register can be changed directly using POP and LDS instructions.

(iv) Extra segment (ES)

 Extra segment is a 16-bit register containing address of 64KB segment, usually with
program data.
 By default, the processor assumes that the DI register references the ES segment in
string 'manipulation instructions.
 ES register can be changed directly using POP and LES instructions.
 It is possible to change default segments used by general and index registers by
prefixing instructions with a CS, SS, DS or ES prefix.

Pointer Registers

1. Stack Pointer (SP)

 Stack pointer is a 16-bit register pointing to program stack.
2. Base Pointer (BP)
 Base pointer is a 16-bit register pointing to data in the stack segment.
 BP register is usually used for based, based indexed or register indirect addressing.

Index Registers:
(i) Source Index (SI)
 Source index is a 16-bit register.
 SI is used for indexed, based indexed and register indirect addressing, as well as a
source data address in string manipulation instructions.
(ii) Destination Index (DI)
 Destination index is a 16-bit register.
 DI is used for indexed, based indexed and register indirect addressing, as well as a
destination data address in string manipulation instructions.

Instruction Pointer (IP)

 Instruction pointer is a 16-bit register. The operation is same as the program counter.
 The IP register is updated by the BIU to point to the address of the next instruction.
 Programs do not have direct access to the IP, but during execution of a program the IP
can be modified or saved and restored from the stack.

Flag register

 Overflow Flag (OF) – It is set if an overflow occurs, i.e., a result is out of range.

 Sign Flag (SF) – It is set if the most significant bit of the result is set.

 Zero Flag (ZF) – It is set if the result is zero.

 Auxiliary carry Flag (AF) – It is set if there is a carry out of bit 3 during addition or
borrow by bit 3 during subtraction. This flag is used exclusively for BCD arithmetic.

 Parity Flag (PF) – It is set to 1 if the low-order 8-bits of the result contain an even number
of 1s.

 Carry Flag (CF) – It is set if carry from or borrow to the most significant bit during last
result calculation.

 Trap Flag (TF) – if set, a trap is executed after each instruction.

 Direction Flag (DF) – Used by string manipulation instructions. If set then string
manipulation instructions will auto- decrement index registers. If cleared, then the index
registers will be auto-incremented.

 Interrupt-enable Flag (IF) - Setting this bit enables maskable interrupts.

Instruction Queue:
 The instruction queue is a First-In-First-out (FIFO) group of registers where 6 bytes of
instruction code is pre-fetched from memory.
 It is being done to speedup program execution by overlapping instruction fetch and
execution. This mechanism is known as PIPELINING.
 If the queue is full, the BIU does not perform any bus cycle. If the BIU is not full and can
store at least 2 bytes and EU does not request it to access memory, the BIU may pre-fetch
instructions.
 If the BIU is interrupted by the EU for memory access while pre-fetching, the BIU first
completes fetching and then services the EU. In case of JMP instruction, the BIU will reset
the queue and. begin refilling after passing the new instruction to the EU.

ALU: Arithmetic and Logic Unit ALU is a 16-bit register. It can add, subtract, increment,
decrement, complement, shift numbers and performs AND, OR, XOR operations.

Control unit: " Generates timing and control signals to perform the internal operations of the
microprocessor

1.3 Signal Description of 8086

Clock signal
Clock signal is provided through Pin-19. It provides timing to the processor for operations. Its
frequency is different for different versions, i.e. 5MHz, 8MHz and 10MHz.
Address/data bus
AD0-AD15. These are 16 address/data bus. AD0-AD7 carries low order byte data and
AD8AD15 carries higher order byte data. During the first clock cycle, it carries 16-bit address
and after that it carries 16-bit data.
Address/status bus
A16-A19/S3-S6. These are the 4 address/status buses. During the first clock cycle, it carries 4-
bit address and later it carries status signals.
S7/BHE
BHE stands for Bus High Enable. It is available at pin 34 and used to indicate the transfer of
data using data bus D8-D15. This signal is low during the first clock cycle, thereafter it is
active.

It is available at pin 32 and is used to read signal for Read operation.

Ready
It is available at pin 22. It is an acknowledgement signal from I/O devices that data is
transferred. It is an active high signal. When it is high, it indicates that the device is ready to
transfer data. When it is low, it indicates wait state.
RESET
It is available at pin 21 and is used to restart the execution. It causes the processor to
immediately terminate its present activity. This signal is active high for the first 4 clock cycles
to RESET the microprocessor.
INTR
It is available at pin 18. It is an interrupt request signal, which is sampled during the last clock
cycle of each instruction to determine if the processor considered this as an interrupt or not.
NMI
It stands for non-maskable interrupt and is available at pin 17. It is an edge triggered input,
which causes an interrupt request to the microprocessor.

This signal is like wait state and is available at pin 23. When this signal is high, then the
processor has to wait for IDLE state, else the execution continues.

It stands for Minimum/Maximum and is available at pin 33. It indicates what mode the
processor is to operate in; when it is high, it works in the minimum mode and vice-a versa.
INTA
It is an interrupt acknowledgement signal and id available at pin 24. When the microprocessor
receives this signal, it acknowledges the interrupt.
ALE
It stands for address enable latch and is available at pin 25. A positive pulse is generated each
time the processor begins any operation. This signal indicates the availability of a valid address
on the address/data lines.
DEN
It stands for Data Enable and is available at pin 26. It is used to enable Transreceiver 8286. The
transreceiver is a device used to separate data from the address/data bus.
DT/R
It stands for Data Transmit/Receive signal and is available at pin 27. It decides the direction of
data flow through the transreceiver. When it is high, data is transmitted out and vice-a-versa.
M/IO
This signal is used to distinguish between memory and I/O operations. When it is high, it
indicates I/O operation and when it is low indicating the memory operation. It is available at
pin 28.
WR
It stands for write signal and is available at pin 29. It is used to write the data into the memory
or the output device depending on the status of M/IO signal.
HLDA
It stands for Hold Acknowledgement signal and is available at pin 30. This signal
acknowledges the HOLD signal.
HOLD
This signal indicates to the processor that external devices are requesting to access the
address/data buses. It is available at pin 31.
QS1 and QS0
These are queue status signals and are available at pin 24 and 25. These signals provide the
status of instruction queue. Their conditions are shown in the following table

S0, S1, S2
These are the status signals that provide the status of operation, which is used by the Bus
Controller 8288 to generate memory & I/O control signals. These are available at pin 26, 27,
and 28. Following is the table showing their status
LOCK
When this signal is active, it indicates to the other processors not to ask the CPU to leave the
system bus. It is activated using the LOCK prefix on any instruction and is available at pin 29.
RQ/GT1 and RQ/GT0
These are the Request/Grant signals used by the other processors requesting the CPU to release
the system bus. When the signal is received by CPU, then it sends acknowledgment. RQ/GT0
has a higher priority than RQ/GT1.
1.4 Physical Memory Organization
Memory Segment
It is a portion of memory that is used to address the data and instructions.
Offset Address
It is a part of the address that is added to the segment address to point to a specific location
inside the segment.
For example: If the segment address is 1000H and offset address is 3000H then the memory
location becomes 13000H (10*1000H + 3000H)
Effective Address
It can be defined as the address of the data operand in the memory. It can be calculated from
the formula
(Effective Address = Segment Register + Offset Address). In 8086 the segment registers are
DS (Data segment), CS (code segment), ES (Extra Segment), SS (Stack segment).
Physical Address
It is defined as the actual address of the data or instruction where it is stored physically in the
memory and calculated by (Physical Address = 10* segment Address + Offset Address).
Segmentation
It is a process of dividing the memory into segments and each segment can have a size of 64Kb
(starting Address-0000H, last Address-FFFFH).
 In 8086 one megabyte is physically organized as an odd bank and an even bank, each
of 512Kbytes, addresses in parallel by a processor. Byte data with even address
transferred on D7-D0, while byte data with odd address is transferred on D15-D8 bus
lines.
 To select an even or odd bank it has BHE and Ao as selector lines. Instruction stream is
fetched from memory as words and is addressed internally by a processor.
If it fetches a word from memory, the different possibilities are
 Both bytes may be data operands
 Both bytes may contain opcode
 One is opcode while other may be data
All these possibilities are taken care of by internal decoder circuit of microprocessor. This
decoder detects the operand and data opcodes and derives the input for timing and control unit.
The timing and control unit then derives signal required for execution of instruction. If the
word is located in even address only one read or write cycle is required and if the word is
located at odd address first read or write required for accessing lower byte while second one is
required for accessing upper byte. Thus, two bus cycles are required if the word is located at
an odd address.
8086 is a 16-Bit microprocessor and hence can access 2 bytes of data in one memory I/O read
or write operation. But commercially available chips are only byte size i.e. they can store only
one byte in memory location. To store 16-Bit data, two successive memory locations are used
and lower byte of 16-Bit microprocessor is stored in first memory location while second byte
is stored in next location.
In 16-Bit read or write operation both of these bytes will read or write in single machine cycle.
A map of 8086 memory system starts at 00000H and ends at FFFFFH. To achieve 16-Bit
transfer using 8-Bit memory, in parallel map of system by the memory address will obviously
be divided into memory bank as shown in the below figure.

16-Bit data is stored at first address of map 00000H and it is to be transferred over D0-D7 of
microprocessor which is in 8-bit memory. Higher byte of 16-bit data is stored in next address
00001H, it is to be transferred over D8-D15 of microprocessor bus.
It is to be observed that all lower bytes are stored at even address and higher address are
stored at odd address. If 8086 transfers a 16-bit data from/to memory both even and odd
banks are selected for 16-bit operation.
Two signals Ao and BHE solve the problem of selection of appropriate memory banks as
shown in the following figure.

Following are the examples to calculate Physical Address:

1.5 Addressing Modes of 8086
The addressing modes specify the location of the operand and also how its location may be
determined. The following addressing modes are supported in the 8086.
 Register Addressing Mode
 Immediate Addressing Mode
 Direct Memory Addressing Mode
 Indirect memory addressing Mode
 Register Indirect Addressing Mode
 Base plus Index Register Addressing Mode
 Register Relative Addressing Mode
 Base plus Index Register Relative Addressing Mode
 String Addressing Mode

Register Addressing Mode

When both destination and source operands reside in registers, the addressing mode is known
as register addressing mode. Following are the examples:
 MOVAX, BX
Move the contents of BX register to AX register. The contents of BX register remain
unchanged.
 AND AL, BL
AND the contents of AL register with the contents of BL register and place the resultant
contents in AL register.
Immediate Addressing Mode
When one of the operands is part of the instruction, the addressing mode is known as immediate
addressing mode. Examples are given below
 MOV CX, 2346H
Copy into CX the 16-bit data 2346H.
 SUB AL, 24H
Subtract 24H from the contents of AL register and put the result in AL register.
Direct Memory Addressing Mode
In this mode, the 16-bit offset address is part of the instruction as displacement field. It is stored
as 16-bit unsigned or 8-bit sign-extended number.
 MOV (4625H), Dl
Copy the contents of DL register into memory locations calculated from Data Segment
register and offset 4625H.
  OR AL, (3030H)
OR the contents of AL register with the contents of memory location calculated from DS
register and offset 3030H.
Indirect Memory Addressing Mode
The effective memory address is stored in a register. Uses BX, BP, SI, or DI to hold the memory
address.
 MOV AL, [BX]
Load AL from the memory location pointed by BX
 MOV [SI], DX
Store DX into the memory location pointed by SI
Register Indirect Addressing Mode
In this addressing mode, the offset address is specified through pointer register or index
register. For index register, the SI (Source Index) register or DI (Destination Index) register
may be used, whereas for pointer register, BX (Base Register) register or BP (Base Pointer)
register may be used.
Following are some examples of the application of the register indirect addressing mode.
 MOV AL, (BP)
Copy into AL register the contents of memory location, whose address is calculated using offset
as contents of BP register and the contents of DS register.
Base plus Index Register Addressing Mode
In this mode, both base register (BP or BX) and index register (SI or DI) are used to indirectly
address the memory location. An example is given below.
 MOV (BX + DI), AL
Copy the contents of AL register into memory location whose address is calculated using the
contents of DS (Data Segment), BX (Base Register) and DI (Destination Index) registers.
Register Relative Addressing Mode
This mode is similar to base plus index addressing mode. In this mode, the offset is calculated
using either a base register (BP, BX) or an index register (SI, DI) and the displacement specified
as an 8-bit or a 16-bit number, as part of the instruction
 MOV AX, (DI + 06)
Copy to AL the contents of memory location whose address is calculated using DS (Data
Segment), DI (Destination Index) register with displacement of 06, and copy to AH the
contents of the next higher memory location.
Base plus Index Register Relative Addressing Mode
This addressing mode is basically the combination of base plus index register addressing mode
and register relative addressing mode. To find the address of the operand in memory, a base
register (BP or BX), an index register (DI or SI) and the displacement which is specified in
instruction is used along with the data segment register. For example:
 MOV (BX + DI + 2), CL
Copy the contents of the CL register to the memory location whose address is calculated using
DS (Data Segment), BX (Base Register) and DI (Destination Index) registers and 02 as
displacement.
String Addressing Mode
In this addressing mode, the string instruction uses index registers implicitly to access memory.
Example: MOVSB Copy the byte from the source string location determined by DS and SI to
the destination string location determined by ES and DI.
1.6 The instruction set of 8086.
Intel 8086 has approximately 117 instructions. These instructions are used to transfer data
between registers, register to memory, memory to register or register to I/O ports and other
instructions are used for data manipulation.
These instructions are classified in to six-groups as follows.
1. Data Transfer Instructions
2. Arithmetic Instructions
3. Bit Manipulation Instructions
4. String Instructions
5. Program Execution Transfer Instructions
6. Processor Control Instructions
1. Data Transfer Instructions

MOV
MOV destination, source
This (Move) instruction transfers a byte or a word from the source operand to the destination
operand.
(DEST) ← (SRC), DEST = Destination, SRC = Source
MOV AX, BX
MOVAX, 2150H
MOV AL, [1135]
PUSH
PUSH Source
This instruction decrements SP (stack pointer) by 2 and then transfers a word from the source
operand to the top of the stack now pointed to by stack pointer.
(SP) ← (SP)-2
((SP) + 1: (SP)) ← (SRC)
PUSH SI
PUSH BX 3.
POP
POP destination
This instruction transfers the word at the current top of stack (pointed to by SP) to the
destination operand and then increments SP by 2, pointing to the new top of the stack.
(DEST) ← ((SP) + 1:(SP)) (SP) ← (SP) + 2
POP DX
POP DS
LAHF
Load Register AH from Flags
This instruction copies Sign flag(S), Zero flag (Z), Auxiliary flag (AC). Parity flag (P) and
Carry flag (C) of 8085 into bits 7, 6, 4, 2 and 0 respectively, of register AH. The content of bits
5, 3 and 1 is undefined.

SAHF
Store Register AH into Flags This instruction transfers bits 7, 6, 4, 2 and 0 from register AH
into S, Z, AC, P and C flags respectively, thereby replacing the previous values

XCHG
XCHG destination, source
This (Exchange) instruction switches the contents of the source and destination operands.
(Temp) ← (DEST) (DEST) ← (SRC) (SRC) ← (Temp)
XCHG AX, BX
XCHG BL, AL
XLAT
XLAT table
This (Translate) instruction replaces a byte in the AL register with a byte from a 256-byte, user-
coded translation table.
XLAT is useful for translating characters from one code to another like ASCII to EBCDIC.
Register BX is the starting point of the table. The byte in AL is used as an index into the table
and is replaced by the byte at the offset in the table corresponding to AL's binary value.
AL ← ((BX) + (AL))
XLAT ASCII_TAB
XLAT Table_3
LEA
LEA destination, source
This (Load Effective Address) instruction transfers the offset of the source operand (memory)
to the destination operand (16-bit general register).
(REG) ← EA
LEA BX, [BP] [DI]
LEA SI, [BX + 02AF H]
LDS
LDS destination, source
This (Load pointer using DS) instruction transfers a 32-bit pointer variable from the source
operand (memory operand) to the destination operand and register DS.
(REG) ← (EA) (DS← (EA+2)
LDS SI, [6AC1H]
LES
LES destination, source
This (Load pointer using ES) instruction transfers a 32-bit pointer variable from the source
operand (memory operand) to the destination operand and register ES.
(REG) ← (EA) (ES) ← (EA+2)
LES DI, [BX]
IN
IN accumulator, port
This (Input) instruction transfers a byte or a word from an input port to the accumulator (AL
or AX).
(DEST) ← (SRC)
IN AX, DX
IN AL, 062H
OUT
OUT port, accumulator
This (Output) instruction transfers a byte or a word from the accumulator (AL or AX) to an
output port.
(DEST) ← (SRC)
OUT DX, AL
OUT 31, AX
2. Arithmetic Instructions

ADD
ADD destination, source
This (Add) instruction adds the two operands (byte or word) and stores the result in destination
operand.
(DEST) ← (DEST) + (SRC)
ADD CX, DX
ADD AX, 1257 H
ADDBX, [CX]
ADC
ADC destination, source
This (Add with carry) instruction adds the two operands and adds one if carry flag (CF) is set
and stores the result in destination operand.
(DEST) ← (DEST) + (SRC) + 1
ADC AX, BX
ADC AL, 8
ADC CX, [BX]
SUB
SUB destination, source
This (Subtract) instruction subtracts the source operand from the destination operand and the
result is stored in destination operand.
(DEST) ← (DEST) - (SRC)
SUB AX, 6541 H
SUB BX, AX
SUB SI, 5780 H 4.
SBB
SBB destination, source
This (Subtract with Borrow) instruction subtracts the source from the destination and subtracts
1 if carry flag (CF) is set. The result is stored in destination operand.
(DEST) ← (DEST) - (SRC) -1
SBB BX, CX
SBB AX, 2 5.
CMP
CMP destination, source
This (Compare) instruction subtracts the source from the destination, but does not store the
result.
(DEST) - (SRC)
CMP AX, 18
CMP BX, CX
INC
INC destination
This (Increment) instruction adds 1 to the destination operand (byte or word).
(DEST) ← (DEST) + 1
INC BL
INC CX
DEC
DEC destination
This (Decrement) instruction subtracts 1 from the destination operand.
(DEST) ← (DEST)-1
DEC BL DEC AX
NEG
NEG destination
This (Negate) instruction subtracts the destination operand from 0 and stores the result in
destination. This forms the 2's complement of the number.
(DEST) ← 0 - (DEST)
NEG AX
NEG CL
DAA
This (Decimal Adjust for Addition) instruction converts the binary result of an ADD or ADC
instruction in AL to packed BCD format.
If the auxiliary carry flag is set or the low 4 bits of AL are greater than 9, then 06 H is added
to AL. If the carry flag is set or the high 4 bits of AL are greater than 9, then 60 H is added to
the AL.
DAS
This (Decimal Adjust for Subtraction) instruction converts the binary result of a SUB or SBB
instruction in AL to packed BCD format.
AAA
This (ASCII Adjust for Addition) instruction adjusts the binary result of ADD or ADC
instruction. If bits 0-3 of AL contain a value greater than 9, or if the auxiliary carry flag (AF)
is set, the CPU adds 06 to AL and adds 1 to AH. The bits 4-7 of AL are set to zero.
(AL) ← (AL) + 6 (AH) ← (AH) +1 (AF) ←1
AAA
AAS
This (ASCII Adjust for Subtraction) instruction adjusts the binary result of a SUB or SBB
instruction.
If D3 - D0 of AL>9,
(AL) ← (AL) – 6
(AH) ← (AH) – 1
(AF) ←1
MUL
MUL source
This (Multiply) instruction multiply AL or AX register by register or memory location
contents.
Both operands are unsigned numbers.
If the source is a byte (8 bit), then it is multiplied by register AL and the result is stored in AH
and AL.
If the source operand is a word (16 bit), then it is multiplied by register AX and the result is
stored in AX and DX registers.
If 8-bit data, (AX) ← (AL) × (SRC)
If 16-bit data, (AX), (DX) ← (AX) × (SRC)
MUL25
MUL CX
MULBL
IMUL
IMUL Source This (Integer Multiply) instruction performs a signed multiplication of the source
operand and the accumulator.
If 8-bit data, (AX) ← (AL) × (SRC)
If 16-bit data, (AX), (DX) ← (AX) × (SRC)
IMUL 250
IMUL BL
AAM
This (ASCII Adjust for Multiplication) instruction adjusts the binary result of a MUL
instruction. AL is divided by 10(0AH) and quotient is stored in AH. The remainder is stored in
AL.
(AH) ← (AL/OAH)
(AL) ← Remainder
DIV
DIV Source
This (Division) instruction performs an unsigned division of the accumulator by the source
operand.
It allows a 16-bit unsigned number to be divided by an 8-bit unsigned number, or a 32-bit
unsigned number to be divided by a 16-bit unsigned number.
If byte (8-bit) operation is performed, the 8-bit quotient is stored to AL and 8-bit remainder is
stored to AH register.
If the source operand is a word (16 bit), the 16-bit quotient is stored in AX and the remainder
is stored in DX register.
For 8-bit data, AX / source
(AL) ← Quotient
(AH) ← Remainder
For 16-bit data, AX, DX / Source
(AX) ← Quotient
(DX) ← Remainder
DIV CX
DIV 321
IDIV
IDIV source
This (Integer Division) instruction performs a signed division of the accumulator by the source
operand.
For 8-bit data, AX / Source
(AL) ← Quotient
(AH) ← Remainder
For 16-bit data, AX, DX/Source
(AX) ← Quotient
(DX) ← Remainder
IDIV CL
IDIVAX
AAD
This (ASCII Adjust for Division) instruction adjusts the unpacked BCD dividend in AX before
a division operation. AH is multiplied by 10(0AH) and added to AL. AH is set to zero.
(AL) ← (AH × 0AH) + (AL)
(AH) ←0
CBW This (Convert Byte to Word) instruction converts a byte to a word. It extends the sign
of the byte in register AL through register AH.
This instruction can be used for 16 bit IMUL or IDIV instruction.

CWD
This (Convert Word to Double word) instruction converts a word to a double word. It extends
the sign of the word in register AX through register DX.
If AX < 8000 H, then DX = 0000 H
If AX > 8000 H, then DX = FFFFH

3. Bit Manipulation Instructions

Logical Instructions: AND, OR, XOR, NOT, TEST
Shift Instructions: SHL, SAL, SHR, SAR
Rotate Instructions: ROL, ROR, RCL, RCR
1.6 Assembler directives and operation
An assembler is a program used to convert an assembly language program into the equivalent
machine code modules which may further converted into executable codes.
Some directives such as ORG, EQU, DB, DW, etc which are common in different assemblers
were also described. Though a representative set of directives for the 8086 assembler is
presented, it is possible that some assemblers have a few additional directives. On the other
hand, some of the directives presented here may not be present or may be present in different
forms. Directives for Constant and Variable Definition An Intel 8086 assembly program uses
different types of constants like binary, decimal, octal and hexadecimal.
These can be represented in the program using different suffixes like B (for binary), D (for
decimal), O (for octal) and H (for hexadecimal) to the constant. For example:
• 10H is a hexadecimal number (equivalent to decimal 16).
• 27O is an octal number (equivalent to decimal 23).
• 10100B is a binary number.
A number of directives are used to define and store different kinds of constants. The DB
(Define Byte), DW (Define Word), DDW (Define Double Word) are described in Chapter The
8086 assembler uses DD as directive for double word. Some of the 8086 assemblers also
provide the following additional directives.
 DQ : Define Quadword
 DT : Define Ten Bytes
In addition, these directives can be used to store strings and arrays. For example:
 NAME DB "NEHA SHIKHA". The ASCII codes of alphanumeric characters specified within
double quotes are stored.
 NUM DB 5, 6, 10, 12, 7. The array of five numbers NUM is declared and the numbers
5, 6, 10, 12 and 7 are stored.
The directives DUP and EQU are used to store strings and arrays. DUP Using the DUP
directive, several locations may be initialized and the values may be put in those locations. The
format is as follows. Name Type Num DUP (value)
For example: TEMP DB 20 DUP (5)
The above directive defines an array of 20 bytes in memory and each location is initialized to
5. The array is named TEMP. EQU The EQU directive may be used to define a data name with
immediate value or another data name. It can also be used to equate a name to a string.
For example: NUMB EQU 20H .
NAME EQU “RASHMI”
Program Location Control Directives
The directives used for program location control in the 8086 assembler are (ORG, EVEN,
ALIGN and LABEL. ORG The ORG directive is used to set the location counter to a particular
value. For example:
 ORG 2375H
The location counter is set to 2375H. If it occurs in data segment, the next data storage will
start at 2375H. If it is in code segment, the next instruction will start at 2375H. EVEN Using
EVEN directive, the next data item or label is made to start at the even address boundary. The
assembler, on encountering EVEN directive, will advance the location counter to even address
boundary. For example:
 EVEN TABLE DW 20 DUP (0)
This statement declares an array named TABLE of 20 words starting from the even address.
Each word is initialized to zero.
 ALIGN number
This directive will force the assembler to align the next segment to an address that is divisible
by 2, 4, 8 or 16. The unused bytes are filled with 0 for data and NOP instruction for code. For
example: ALIGN 2
It will force the next segment to the next even address.
 LENGTH
It is an operator which is used to tell the assembler to determine the number of elements in a
data item, such as string or array. For example: MOV CX, LENGTH ARRAY
This statement will move the length of the array to the CX register. OFFSET This operator is
used to determine through the assembler, the offset of a data item from the start of the segment
containing it. For example: MOV AX, OFFSET FACT
This statement will place in the AX register the offset of the variable FACT from the start of
the segment.
 LABEL
The LABEL directive is used to assign a name to the current value in the location counter. The
location counter is used by the assembler to keep track of the current location. The value in the
location counter denotes the distance of the current location from the start of the segment.

Segment Declaration Directives

These directives help in declaring various segments with specific names. The start and the end
of segments may also be specified using this directive. The directives for segment declaration
include SEGMENT, ENDS, ASSUME, GROUP, CODE, DATA, STACK etc.
SEGMENT and ENDS
The SEGMENT and ENDS directives signify the start and end of a segment. INST SEGMENT
ASSUME CS: FNST, DS: DATAW
_________
_________
INST ENDS ASSUME
This directive is used to assign logical segment to physical segment at any time. It tells the
assembler as to what addresses will be in segment registers at the time of execution.
For example:ASSUME CS: CODE, DS: DATA, SS: STACK
This directive tells the assembler that the CS register will store the address of the segment
whose name is CODE, and so on.
.CODE (Name) This code directive is the shortcut used in the definition of code segments.
The name is optional and is specified if there is more than one code segment in the program.
.DATA and .STACK Similar to .CODE, the .DATA and .STACK directives are shortcuts in
the definition of data segment and stack segment, respectively.
GROUP This directive is used to tell the assembler to group all the segments in one logical
group segment. This allows the contents of all the segments to be accessed from the same
segment base. For example:
PROG GROUP CODE, DATA
The above statement will group the two segments CODE and DATA into one segment named
PROG. Each segment must be declared using ASSUME statement as in the following
statement.
ASSUME CS: PROG DS: PROG
TITLE This directive is also used for the listing of the program. The title declared in this
directive defines the title of the program and is listed in line 2 of each page of program listing.
The maximum number of characters allowed is 60.
For example: TITLE PROGRAM TO FIND SQUARE ROOT
NAME The NAME directive is used to assign a specific name to each module, when the
program consists of a number of modules. This helps in understanding the program logic.
END This is the last statement of the program and it specifies the end of the program to the
assembler. It must be noted that not all of the above directives are used in all programs. User
may deploy them depending on the need of the program logic.
1.7 interrupts processing
Interrupts: A signal to the processor to halt its current operation and immediately transfer
control to an interrupt service routine is called as interrupt. Interrupts are triggered either by
hardware as when the keyboard detects a key press, or by software, as when a program executes
the INT instruction.
 Interrupts are triggered by different hardware; these are called hardware interrupts.
 To make a software interrupt there is an INT instruction, it has very simple syntax: INT
Value.
Where value can be a number between 0 to 255 (or 00 to FF h).
Interrupt Service Routings (ISRs) IST is a routing that receives processor control when a
specific interrupt occurs.
The 8086 will directly call the service routing for 256 vectored interrupts without any software
processing. This is in contrast to non-vectored interrupts that transfer control directly to a single
interrupt service routine, regardless of the interrupt source. The 8086 provides a 256 entry
interrupt vector table beginning at address 0:0 in memory. This is a 1K table containing 256 4-
byte entries. Each entry in the table contains a segmented address that points at the interrupt
service routing in memory. Generally, interrupts referred by their index into this table, so
interrupt zero‟s address (vector) is at memory location 0:0 interrupt one‟s vector is at address
0:4, interrupt two‟s vector is at address 0:8, etc.

Interrupt vector table: It is a table maintained by the operating system. It contains addresses
(vectors) of current interrupt service routine. When an interrupt occurs, the CPU branches to
the address in the table that corresponds to the interrupt‟s number. When an interrupt occurs,
regardless of source, the 8086 does the following:
1. The CPU pushes the flags register onto the stack.
2. The CPU pushes a far return address (segment: offset) onto the stack, segment value first.
3. The CPU determines the cause of the interrupt (i.e, the interrupt number) and fetches the
four byte interrupt vector from address 0 : vector x 4 (0:0, 0;4, 0:8 etc)
4. The CPU transfers control to the routine specific by the interrupt vector table entry.
After the completion of these steps, the interrupt service routine takes control. When the
interrupt service routine wants to return control, it must execute an IRET (interrupt return)
instruction. The interrupt return pops the far return address and the flags of the stack.

Types of Interrupts :
1. Hardware Interrupt – External used INTR and NMI
2. Software Interrupt – Internal – from INT or INTO
3. Processor Interrupt – Traps and 10 Software Interrupts
External – generated outside the CPU by other hardware, (INTR, NMI)
Internal – generated within CPU as a result of an instruction of operation (INT, INTO, Divide
error and single step)
Dedicated Interrupts:
(i) Divide Error Interrupt (Type 0)
This interrupt occurs automatically following the execution of DIV or IDIV instruction when
the quotient exceeds the maximum value that the division instruction allows.
(ii) Single Step Interrupt (Type 1)
This interrupt occurs automatically after execution of each instruction when the Trap Flag (TF)
is set of 1. It is used to execute programs one instruction at a time, after which an interrupt is
requested
(iii)Non Maskable Interrupt (Type 2)
It is the highest priority hardware interrupt that triggers on the positive edge. This interrupt
occurs automatically when it received a low-to-high transition on its NMI input pin. This
interrupt cannot be disabled or masked. It is used to save program data or processor status in
case of system power failure.
(iv) Breakpoint Interrupt (Type 3)
This interrupt is used to set break point is software debugging programs.
(v) Overflow Interrupt (Type 4)
This interrupt is initiated by INTO (Interrupt on Overflow) instruction. It is used to check
overflow condition after any signed arithmetic operation in the system. The overflow flag (OF)
will be set if the signed arithmetic operation generates a result whose size is larger than the size
of destination register or memory location. At this time overflow interrupt is used to indicate
an error condition.
Software Interrupts (INT n) The software interrupts are non maskable interrupts. They are
higher priority than hardware interrupts.
The software interrupts are called within the program using the instruction INT n. Here „n‟
means value and is in the range of 0 to 255. These interrupts are useful for debugging, testing
ISRs and calling procedures.
Hardware Interrupts INTR and NMI are called hardware interrupts. INTR is maskable and
NMI is non maskable interrupts. INTR interrupts (type 0-255) can be used to interrupt a
program execution.
This interrupt is implemented by using two pins: INTR and INTA. This interrupts can be
enabled or disabled by STI (IF=1) or (IF=0) respectively.
Interrupt Priority The priority of interrupts of 8086 is shown in Table. The software interrupts
except single step interrupt have the highest priority; followed by NMI, followed by INTR.
Single step interrupt has the least priority. The 8086 checks for internal interrupts before for
any hardware interrupt. Therefore, software interrupts have higher priority than hardware
interrupts.
 1.8 Numeric Data Processor 8087

8087 numeric data processor is also known as Math co-processor, Numeric processor
extension and Floating point unit. It was the first math coprocessor designed by Intel to pair
with 8086/8088 resulting in easier and faster calculation.

Once the instructions are identified by the 8086/8088 processor, then it is allotted to the 8087
co-processor for further execution.

The data types supported by 8087 are −

 Binary Integers
 Packed decimal numbers
 Real numbers
 Temporary real format

The most prominent features of 8087 numeric data processor are as follows −

 It supports data of type integer, float, and real types ranging from 2-10 bytes.
 The processing speed is so high that it can calculate multiplication of two 64-bits real numbers
in ~27 µs and can also calculate square-root in ~35 µs.
 It follows IEEE floating point standards.

8087 Architecture

8087 Architecture is divided into two groups, i.e., Control Unit (CU) and Numeric Extension
Unit (NEU). The control unit handles all the communication between the processor and the
memory such as it receives and decodes instructions, reads and writes memory operands,
maintains parallel queue, etc. All the coprocessor instructions are ESC instructions, i.e., they
start with ‘F’, the coprocessor only executes the ESC instructions while other instructions are
executed by the microprocessor.

The numeric extension unit handles all the numeric processor instructions like arithmetic,
logical, transcendental, and data transfer instructions. It has 8 register stack, which holds the
operands for instructions and their results.

The architecture of 8087 co-processor is as follows –

8087 Pin Description

Let us first take a look at the pin diagram of 8087 –

The following list provides the Pin Description of 8087 −

AD0 – AD15 − These are the time multiplexed address/data lines, which carry addresses
during the first clock cycle and data from the second clock cycle onwards.

A19 / S6 – A16/S − These lines are the time multiplexed address/status lines. It functions in a
similar way to the corresponding pins of 8086. The S6, S4 and S3 are permanently high,
while the S5 is permanently low.

BHE/S7 − During the first clock cycle, the BHE/S7 is used to enable data on to the higher
byte of the 8086 data bus and after that works as status line S7.

QS1, QS0 − These are queue status input signals which provides the status of instruction queue,
their conditions as shown in the following table

INT − It is an interrupt signal, which changes to high when an unmasked exception has been
received during the execution.

BUSY − It is an output signal, when it is high it indicates a busy state to the CPU.

READY − It is an input signal used to inform the coprocessor whether the bus is ready to
receive data or not.

RESET − It is an input signal used to reject the internal activities of the coprocessor and prepare
it for further execution whenever required by the CPU.

CLK − The CLK input provides the basic timings for the processor operation.
VCC − It is a power supply signal, which requires +5V supply for the operation of the circuit.

S0, S1, S2 − These are the status signals that provide the status of the operation which is used
by the Bus Controller 8087 to generate memory and I/O control signals. These signals are
active during the fourth clock cycle.

RQ/GT1 & RQ/GT0 − These are the Request/Grant signals used by the 8087 processors to
gain control of the bus from the host processor 8086/8088 for operand transfers