Enhanced TDMA Based High Speed Bus Arbitrarion

Pankaj Dobwal (MTvlsi 2011 20) Harsh vishakarma (MTvlsi 2011 11

ABV Indian Institute Of Information Technology and Management, Gwalior, India (An Autonomous Institute Of Govt. Of India)

April 23, 2012

Table of contents

Table of contents

1. Introduction 2. Problem Denition 3. Proposed Solution 4. Implementation 5. Mathematical Proof 6. Eciencies comparison 7. Conclusion 8. References

Intoduction

Introduction
Multiprocessor system has an inherent problem of communication overhead between processors. It depends on how we are distributing the program for execution on dierent processors. If we are able to develop a very ecient method for interprocessor communication than we can minimize the communication overhead and so system performance. In general processor communicate through a common shared bus. The bus uses the access policy to provide access on bus for sending and receiving the data/information among the processors. Many multiprocessor uses time division multiple access (TDMA) method for this purpose, In which each processor is allotted a time slot in which that can access to the bus.

Intoduction

Inteoduction cont..
For this purpose system maintains a bus arbitration which includes the information that a particular time which processor is granted the bus. Here the bus arbitration schedule is predetermined and so it is static. We are providing a new concept of TDMA bus access called as Enhanced TDMA bus access method which uses a dynamic bus arbitration schedule Here the bus access policy is TDMA but it is changing according to the current system needs. We are illustrating this using a two processor model which can be scaled as needed. The main benet of this approach is that it will provide performance greater than or equal to existing system using the static arbitration bus schedules.

Problem defination

Problem denation
TDMA-based bus arbitration policy is suitable for modern system-on-chip designs with QoS constraints. This policy is used in many systems now days. The behavior of the bus arbiter is dened by the bus schedule, consisting of sequences of slots. A bus schedule is divided into segments, and each segment consists of a round, that is, a sequence of slots, that is repeated periodically. This is static means that the policy can not be changed during the run time

Problem defination

Problem denation cont..

The main problems in using this static bus arbitration policy is:
1. Traditional scheme of using static bus arbitration policy may cause underutilization of system resources as slots allotted to CPU- bound job processor are likely to be empty 2. It has static bus schedule so does not take in account the behavior of application at run time.

Conventional TDMA or static bus arbitration policy (for two processors)

P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2

Figure :

Then number indicates the corresponding allotted slot of the processor.

PROPOSED SOLUTION

Proposed solution
We are proposing a solution of the above problems using a dynamic bus arbitration schedule. We are considering the hardware as shown in gure for our illustration purpose. This include1. 2. 3. 4. Two CPU with there private caches A common bus used for interprocessor communication Each processors private memory A shared memory, which uses write through policy to overcome the cache coherence problem.

PROPOSED SOLUTION

Proposed solution cont..

Use of dynamic bus schedule which can change according to run time behavior of the application as1. If a processor is allotted some I/O bound job and another processor CPU bound job than slots of CPU bound job processor are likely to used by I/O bound job processor. 2. So delay in accessing the bus can be reduced. Further sequencing is swapped as the CPU which using bus currently is likely to not use the next slot/slots.

Suppose that the time slots have equal intervals.

2 1

1/2

1 2

1 2

Figure :

PROPOSED SOLUTION

Proposed solution cont..

Here 1 and 2 denotes the corresponding processors i.e. 1 for P1 and 2 for P2 respectively. At t=0 system starts the execution and at t=1 bus is allotted to CPU-1 after that turn of CPU-2 comes and it uses the bus. At t=3 again CPU-1 is allotted the bus and at t=4 CPU-2 is accessing the bus. Now suppose at t=5 CPU-1 do not want to use the bus. If it was a static bus schedule than this slot was wasted here we are assuming that CPU-2 is allotted an I/O bound job and want to use the bus.

PROPOSED SOLUTION

Proposed solution cont..

We are now modifying our bus schedule in such a way that CPU-1 do not want to use the bus but CPU-2 wants access to the bus so the bus is granted to CPU-2 and further sequencing is swapped. This swapping is done as it may possible that in next slot CPU-1 wants to use the bus if dont than again swapping is done. At t=5 the bus is granted to CPU-2 this procedure is leading to either increased system performance or leaving it same as static bus arbitration policy. The overall turn around time of the processes can be reduced to some extent.

Implementation

Implementation

For implementing the above explained procedure we are using the same hardware as explained, but with dynamic bus arbitration schedule. Assumption1. 2. 3. 4. Bus slots are of equal length. jobs are distributed evenly to the processors bus id idle if no processor is using the bus swapping is done in linear time as this requires changing of pointers

Here is a ow chart which shows how this method works-

Implementation

Implementation

Figure :

Mathematical Proof

Mathematical proof
Conventional Method: This not considers the run time behavior of the application. Let
1. N be the number of slots required to complete a task which is evenly distributed to two processors. 2. N1 is the numbers of slots allotted to processor P1 3. N2 is the number of slots allotted to processor P2 4. Ne is the total number of idle slots 5. As the slots may go idleTotal time taken to accomplish a task is N 6. And as this is the static schedule and slots are allotted equally So, 7. N1 = N2 = (N/2 Ne) 8. And N = N1 + N2 + Ne 9. which is the total completion time of task...........................(i)

Mathematical Proof

Proof cont..

Enhanced TDMA bus access method: This considers the run time behavior of the application.
1. Let N is the total number of slots required to accomplish the given task 2. N1 is the total number of slots used by the P1 Processor. 3. N2 is the total number of slots used by the P2 Processor. 4. Ne is the number of idle slots. 5. S is the overhead to swap the pointers So the total execution time in this caseN can be calculated as6. N = N1 + N2 + S + Ne ...........(ii)

Mathematical Proof

Proof cont..
NOTE- Here N1 and N2 are the allotted slots where asN1 and N2 are used slots. For this method to be ecient than N <= N should be hold According to ow chart number of idle slots in second case is denitely<=number of idle slots in case one.
Means Ne <= Ne Overhead in swapping is vary as this is implemented in hardware and requires only changing of pointers. So let assume S to be negligible as compared to time interval of slots. Also asN1 andN2 are used slots so denitely we can conclude that N1 <= N1, and N2 <= N2...................(iii) This is equal if task is doing excessive I/O activity rather then computing. For real time applications equation (iii) holds.

Mathematical Proof

Proof cont..

So nally we can conclude that N1 + N2 + Ne N1 + N2 + Ne. In general these are not equal and so, N1 + N2 + Ne < N1 + N2 + Ne..............................(iv ) Assuming S to be negligible we can say from equation (iv) that N N So, Enhanced TDMA bus access method is more ecient than that of conventional TDMA which uses the static bus arbitration schedule. This completes the proof.

Eciencies comparison

Eciency comparison
Let 1 is the eciency of the conventional TDMA method than 1 = used slots/ total number of slots so, 1 = (N1 + N2) (N1 + N2 + Ne)

2 = from equation (iii)

(N1 + N2 ) (N1 + N2 + Ne )

(N1 + N2) = k1 (N1 + N2 ), where k1 >= 1 Also from equation (iv)

Eciencies comparison

Eciency comparison
(N1 + N2 + Ne) = k2 (N1 + N2 + Ne ) , K 2 >= 1 So from equation (v) 1 = 1/2 = k1/k2 2 = (k2/k1) 1 or 2 = k 1 here k >= 1 as N1 + N2 + Ne <= N1 + N2 + Neand also Ne <= Ne . when k = 1than there is no improvement in eciency. k1 (N1 + N2 ) k2 (N1 + N2 + Ne )

Conclusion

Conclusion

The Enhanced TDMA (ETDMA) bus access method is more ecient than conventional TDMA bus access method. This procedure is also scalable and can be generalized for the n processor architectures. Also ETDMA works good if we have the combination of CPU bound job and I/O bound jobs, means it works good in the application has good job mixing. It is guaranteed in this type of system that they will never perform less than that of the conventional TDMA method.

Refrences

Refrences
Shah, H.; Raabe, A.; Knoll, A.; , Priority division: A high-speed shared-memory bus arbitration with bounded latency, Design, Automation Test in Europe Conference Exhibition (DATE), 2011, vol., no., pp.1-4, 14-18 March 2011 Jakob Ros n, Petru Eles, Zebo Peng and Alexandru Andrei,Predictable Worst-Case Execution Time Analysis for Multiprocessor,2011 Sixth IEEE International Symposium on Electronic Design, Test and Application,pp-99-104,2011. Jakob Ros n, Alexandru Andrei, Petru Eles, Zebo Peng Bus Access Optimization for Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip ,28th IEEE International Real-Time Systems Symposium.pp49- 52,2007. P. Puschner and A. Burns,A Review of Worst-Case Execution-Time Analysis, Real-Time Systems, vol. 2/3, pp.