Nuclear Instruments and Methods in Physics Research A 491 (2002) 233243

Development of the CARIOCA front-end chip for the LHCb muon detector
W. Boniventoa,b,*, P. Jarrona, D. Moraesa,c, W. Rieglera, F. dos Santosa
a CERN, EP-Division, CH-1211 Geneva 23, Switzerland Instituto Nazionale di Fisica Nucleare, Sezione di Cagliari, Cagliari, Italy c LAPE-IF/UFRJ, CP 68528 Cidade Univ., BR-21945970 Rio de Janeiro, Brazil b

Received 21 February 2002; received in revised form 25 April 2002; accepted 29 April 2002

Abstract CERN and Rio Current-mode Amplier is an ampliershaperdiscriminator chip, developed in 0:25 mm CMOS radiation tolerant technology for the readout of the LHCb muon wire chambers. This paper presents the design and test of three prototype chips, including positive and negative pre-amplier, differential shaper, differential discriminator and LVDS driver circuits. r 2002 Elsevier Science B.V. All rights reserved.
PACS: 29.40.Gx; 85.40.e; 07.50.Qx Keywords: CMOS; Readout electronics; Muon detectors

1. Introduction The LHCb muon detector system will consist of ve stations of chambers. The rst station is located in front of the electromagnetic calorimeter while the other four are located behind the calorimeters and are separated one from the other by iron walls [1]. Most of the muon system will be equipped with multi-wire proportional-chambers (80 000 channels).

*Corresponding author. CERN, EP-Division, CH-1211 Geneva 23, Switzerland. Tel.: +41-22-767-8965; fax: +41-22767-8350. E-mail addresses: [email protected] (W. Bonivento), [email protected] (D. Moraes).

One of the purposes of the muon system is to give the Level 0 trigger for muons coming from b-avoured hadron decays. To do this, the trigger requires for a muon candidate to re all ve stations with unambiguous bunch-crossing identication with an efciency of 95% for the muons inside the acceptance. This implies that the chambers in a station should measure the arrival time of muons to better than 3 ns r.m.s. The chamber signal, corresponding to 100 primary electrons on average, is characterized by a fast rising edge, a long 1=t 1:5 tail, where t is the time in ns, going over into a DC current lasting for about 20 ms: The signal has to be shaped to a unipolar narrow pulse in order to cope with the high rates expected in the experiment and limit the dead time

0168-9002/02/$ - see front matterr 2002 Elsevier Science B.V. All rights reserved. PII: S 0 1 6 8 - 9 0 0 2 ( 0 2 ) 0 1 1 6 6 - X

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of the trigger. A detector gas gain of 105 together with an amplier peaking time of 1015 ns was found to be the optimum working point for this detector. For fast shaping, it is convenient to dene input charge as the charge that gives the same output pulse height of a delta-like input signal. With this denition, which will be used through the whole paper, the input charge for an average chamber signal is about 50 fC: In order to allow the desired threshold at about 20% of the average signal, the equivalent noise charge at the input (ENC) should not exceed 2 fC up to the largest detector capacitance of 250 pF: The tail cancellation circuit should work properly for at least 99% of chamber signals, i.e. up to 250 fC input charge. A baseline restoration circuit is needed to compensate for baseline shifts and uctuations. The input impedance of the amplier should be smaller than 50 O to limit the cross-talk due to capacitive coupling. The detector will be subject to a harsh radiation environment. In the inner part of station 1 this will be dominated by charged particles and will correspond to a total accumulated dose of 1 MRad during the life of the experiment. Therefore, a radiation tolerant chip technology is required. Chip specications are summarized in Table 1. To satisfy these requirements, the CERN and Rio Current-mode Amplier (CARIOCA) chip was developed. It was implemented in 0:25 mm CMOS radiation tolerant technology.

The main novelty of the CARIOCA chip lies in the current-mode pre-amplier circuit, which is of new conception. The positive pre-amplier circuit was successfully tested with two prototype chips produced during the year 2000, as described in Ref. [2]. This paper presents the design and test of three new prototype chips, produced during the year 2001 to evaluate, with a step by step approach, the design of both polarity pre-ampliers, shaper, discriminator and LVDS driver circuits. A nal prototype, including a baseline restoration circuit, was submitted to the manufacturer at the end of 2001 and will be the subject of a future publication.

2. Circuit design 2.1. Prototype I negative input polarity preamplier This chip is an eight-channel circuit and was designed for negative input polarity signals. Each channel consists of a current pre-amplier followed by an analog buffer, as shown in Fig. 1. The pre-amplier input stage (see Fig. 2) is a cascode (N1), followed by a voltage to current converter (N0) and a current mirror (N2N3). The input transistor is an NMOS device of 0:7 mm length and 1600 mm width, corresponding to an input capacitance of 6 pF: This transistor operates in moderate inversion and has 42 mA=V transconductance (gm ) at a drain current of about 3:2 mA: The current mirror feeds the current both to the output stage (N4) and back to the input stage. The current gain of the pre-amplier is given by the transconductance ratio of transistors N3

Table 1 Chip specications Delta peaking time at discriminator input Equivalent noise charge at the input Input impedance Shaping circuit o15 ns at Cdet 250 pF o2 fC at Cdet 250 pF o50 O Unipolar with tail cancellation Up to 250 fC o1 ns for input charge > 20 fC 1 MRad

Iin

Out preamp Buffer

Discriminator time walk Radiation resistance

Fig. 1. Block diagram of one channel of prototype I.

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Vdd
Iin preamp Out+ InA Shaper InB Out Iin preamp
Buffer Buffer

I1

N2

N3

N4

N0 Cfeed Vg Iout Iin N1 I2

Fig. 3. Block diagram of one channel of prototype II.

I3

Vdd
GND
Fig. 2. Simplied schematics of the CARIOCA negative input polarity pre-amplier circuit (prototype I).

I1

I2

I3

and N4, which is of about 6. The output current is nally converted into voltage by a resistor (R). A compensating capacitor (Cfeed ) was added to the circuit to improve stability. From PSPICE simulation, the corner frequency (3 dB crossing) was 16 MHz and the input impedance smaller than 50 O inside the bandwidth. 2.2. Prototype II - positive input polarity preamplier and shaper This chip is a four-channel positive input polarity circuit, fully differential. Each channel consists of two pre-ampliers, one connected to the detector and one dummy, i.e. with oating input, a differential shaper and two analog buffers, as shown in Fig. 3. The dummy amplier provides the correct DC voltage at shaper input and helps in power supply rejection. Its noise contribution is small due to the absence of detector capacitance at the input. A simplied schematics of the positive input polarity pre-amplier circuit is shown in Fig. 4. The design of the positive and negative polarity ampliers is very similar. The main difference is the replacement of PMOS transistors by NMOS

Iout

Cfeed

N0 Vg

Iin N1 N2 N3 N4

GND
Fig. 4. Simplied schematics of the positive input polarity preamplier circuit.

transistors in the output stage. From PSPICE simulation, the corner frequency was 23 MHz and the input impedance again smaller than 50 O inside the bandwidth. The shaper circuit [3] is a folded cascode differential amplier with common-mode feedback. A simplied schematic is shown in Fig. 5. Not to degrade the high-frequency performance of the pre-ampliers, the dominant high-frequency pole of the shaper was set to at 160 MHz: Tail cancellation is performed by a double polezero compensation network [4,5], displayed in

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I1

I2

Iin

preamp Out+

C
R R
Vcm

InA
InA
N4 Pole/zero comp

InB

Vcm
Out
+

Shaper
Out I6

Discriminator

LVDS

InB Iin
preamp

Out C

I3

I4

I5

GND

Fig. 7. Block diagram of one channel of prototype III.

Fig. 5. Simplied schematics of the shaper circuit.

Pole/zero comp

20K

2p

1.1p

2.7K 14k
Fig. 6. Schematics of the pole/zero compensation network of the shaper.

Fig. 6, with transfer function Hs s 1=t1 s 1=t3 s 1=t2 s 1=t4 1

The pre-amplier and shaper circuits were already described above. The differential output of the shaper is AC coupled to the discriminator input. In this way the DC voltage at discriminator input is set through the common-mode voltage VCM : The discriminator, whose design was based on an existing circuit [6], is a high-gain differential amplier with symmetric currentmirror loads. A simplied schematic is shown in Fig. 8. The threshold voltage is set in a differential way: the voltages VrefA and VrefB unbalance the current through the main differential pair. The bias current I1 is supplied from an external input through a current mirror connected to the main pair N1N2. Hysteresis is given by a second differential pair N5N6, which contributes to the unbalanced current on the main differential pair. The amount of hysteresis is programmable by means of a current source (I3 ), which shifts the effective discriminator threshold.

3. Measurements 3.1. Experimental setup Each chip was tested with a specic custom made board. The boards for the analog output chips (prototypes I and II) were provided with a wide-bandwidth operational amplier in the noninverting conguration to display on the oscilloscope the true output signal from the chip. For the digital output chip (prototype III), the LVDS output was terminated with a 100 O resistor on the

where t1 9 ns; t2 2:6 ns; t3 80 ns and t4 40 ns: 2.3. Prototype IIIpositive input polarity preamplier, shaper, discriminator and LVDS driver This chip contains a four-channel positive input polarity pre-amplier, followed by shaper and discriminator, fully differential. A block diagram of one channel is shown in Fig. 7.

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P7

P5

P3

P1

P2

P4

P6

P8

N5

N6

VrefA OutA
P11 P9

I3
N3 N4

VrefB
P10 P12

OutB InA
N1 N11

N13

I2

N2

InB
N12 N14

N9

N7

I1

N8

N10

Fig. 8. Simplied schematic of the discriminator circuit.

board and was directly read by the scope through a high impedance probe. The chip was supplied with 2:5 V and the channels were independently provided with all necessary bias currents by resistors on the board. To minimize parasitics, the chips were directly bonded on the board. The test setup consisted of a pulse generator, a board housing the chip and a digital scope, all run with the LABVIEW program on a computer with GPIB interface. A voltage step function of 800 ps rise-time, sent through a series injection circuit, was used as input signal. Two types of injection circuits were used: a series capacitor for delta input signal and a four resistor-capacitor network for 1=t input signal. The 1=t signal injection circuit was calibrated in charge with respect to the other one assuming that equal input charge gives output signals of equal amplitude. In this way, the ballistic decit for the 1=t pulse was neglected (see discussion in Section 3.4). A discrete capacitor on the board was used to simulate the detector capacitance to ground. The parasitic capacitance due to board connections was measured with a capacitance meter to be about 10 pF: This value was included in the experimental results. The range of detector capacitances considered in the measurements was up to 220 pF: Circuit parameters in the range relevant for chip operation in LHCb were measured and compared to PSPICE simulation.

For the analog output chips, gain and peaking time were measured through the oscilloscope curve display. ENC was obtained from the ratio of output signal r.m.s., as calculated by the digital oscilloscope with no input signal, and sensitivity, measured at an input charge of 10 fC; i.e. the nominal threshold for the LHCb wire chambers. For the digital output chip, effective threshold (given as equivalent charge at the input) and ENC were obtained from S-curve measurement, i.e. measuring threshold ring probability for various input charges at xed input threshold. Time delay, dened as the time difference between input signal and threshold crossing of the output signal leading edge, was measured for both analog and digital output pulses. For the analog signal, the time of threshold crossing was obtained by software. Cross-talk in the chip itself was measured removing the bonding wires from all input channels but the injection one. For the analog output chip, cross-talk was dened as the inverse ratio of maximum pulse height on the injection channel and on the neighbour ones. For the digital output chip, it was dened as the ratio of effective thresholds, for a given input threshold. The prototypes described in this paper were meant for testing step by step the various stages of the circuit. Due to lack of time, only a small number of chips per type were measured.

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3.2. Prototype I - negative input polarity preamplier Fig. 9 shows the output pulse shape of the negative input polarity amplier chip for delta and 1=t input signals, at 68 pF detector capacitance and 34 fC input charge. The 1=t signal gives rise to an output pulse with a very long tail. Fig. 10(a) shows the measured signal amplitude vs. input charge at 27 pF (full squares) and 220 pF (full triangles) detector capacitance. The linear ts

up to 150 fC are superposed. Their slopes give a sensitivity of 4.4 and 2:5 mV=fC for 27 and 220 pF detector capacitance, respectively. A maximum non linearity of about 10% is observed at 250 fC and 27 pF detector capacitance. However, it should be noticed that linearity for our application is not a stringent requirement and only tail cancellation at large input charge is an issue. Signal amplitude vs. detector capacitance is shown in Fig. 10(b), for 36 fC input charge signal.

Fig. 9. Output pulse shape (average of 1000 pulses) of the negative input amplier chip for delta (a) and 1=t (b) input signals, at 68 pF detector capacitance and 34 fC input charge. The horizontal scale is 50 ns per division and the vertical scale is 20 mV per division.

160 140

0.8 Signal Amplitude [mV] 250 Signal Amplitude [V]

120 100 80 60 40 20

0.6

0.4

0.2

0 0 50

(a)

100 150 200 Input Charge[fC]

(b)

25 50 75 100 125 150 175 200 225 Detector Capacitance [pF]

Fig. 10. (a) Measured signal amplitude vs. input charge at 27 pF (full squares) and 220 pF (full triangles) detector capacitance. The linear ts up to 150 fC are superposed. (b) Measured (full circles) and simulated (open circles) signal amplitude vs. detector capacitance at 36 fC input charge for the negative input polarity amplier.

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Peaking time vs. detector capacitance at 36 fC input charge is shown in Fig. 11(a) and ranges from 7 to 17 ns: A linear t to the measured ENC vs. detector capacitance Cdet ; shown in Fig. 11(b), gives ENC 975e 48e Cdet pF: Cross-talk in the chip was measured to be 0.8% for the neighbour channel and smaller than 0.1% for the next to neighbour one. Channel-to-channel uniformity, measured on all channels of three chips with a 34 fC delta input

charge pulse and 68 pF detector capacitance, was 3.5% peak to peak for the sensitivity and 5% peak to peak for the peaking time. 3.3. Prototype II - positive input polarity preamplier and shaper Fig. 12(a) shows the measured signal amplitude vs. input charge at 27 pF (full squares) and 220 pF (full triangles) detector capacitance, of the shaper chip positive output. The differential sensitivity

25 22.5 20 17.5 Peaking time [ns] 15 12.5 10 7.5 5 2.5 0 0 250 50 100 150 200 Detector Capacitance [pF] Equivalent noise charge[e] 14000 12000 10000 8000 6000 4000 2000 0

(a)

(b)

25 50 75 100 125 150 175 200 225 Detector Capacitance [pF]

Fig. 11. (a) Measured (full circles) and simulated (open circles) peaking time at 36 fC input charge and (b) measured equivalent noise charge vs. detector capacitance for the negative input polarity amplier.

200 1 180 160 Signal Amplitude [mV] 250 0.8 Signal Amplitude [V] 140 120 100 80 60 40 20 0 0 50 100 150 200 Input Charge[fC] 0 0 25 50 75 100 125 150 175 200 225 Detector Capacitance [pF]

0.6

0.4

0.2

(a)

(b)

Fig. 12. (a) Measured signal amplitude vs. input charge at 27 pF (full squares) and 220 pF (full triangles) detector capacitance. A linear t is superposed. (b) Measured (full circles) and simulated (open circles) signal amplitude vs. detector capacitance at 36 fC input charge for the shaper chip positive output.

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14 12 10 Peaking time [ns] 8 6 4 2 0 Equivalent noise charge[e] 0 25 50 75 100 125 150 175 200 225 250 Detector Capacitance [pF] 16000 14000 12000 10000 8000 6000 4000 2000 0 0 50 100 150 200 Detector Capacitance [pF] 250

(a)

(b)

Fig. 13. Measured (full circles) and simulated (open circles) peaking time at 36 fC input charge and measured equivalent noise charge vs. detector capacitance for the shaper chip positive output.

can be obtained by multiplying the positive output value by a factor of 2. The linear ts up to 150 fC are superposed. Their slopes give a sensitivity of 4.3 and 1:4 mV=fC for 27 and 220 pF detector capacitance, respectively. A maximum nonlinearity of about 20% is observed at 250 fC and 27 pF detector capacitance, about a factor of 2 larger than the negative pre-amplier alone. Signal amplitude of the shaper chip positive output vs. detector capacitance is shown in Fig. 12(b), for an input charge of 36 fC: Peaking time for the shaper chip positive output, shown in Fig. 13(a), ranges from 6.5 to 10:5 ns: The different peaking times compared to the negative pre-amplier chip are consistent with the different bandwidth, as discussed in Section 2.2. ENC vs. detector capacitance is shown in Fig. 13(b). A linear t gives ENC 2837e 52e Cdet pF: Signal output for 1=t signal input at 280 fC input charge and 56 pF of detector capacitance is shown in Fig. 14. It is clear that the output signal is not exactly differential, the sum not being zero. However, tail cancellation is not spoiled at large input charge: indeed, the output signal width is less than 30 ns: The output signal displays an overshoot of about 40 ns after the main peak which is due to the approximation error of the tail cancellation circuit to a true 1=t pulse. This effect is also shown by the simulation.

Fig. 14. Measured shaper output (average of 1000 pulses) for a 280 fC; 1=t pulse input and 56 pF detector capacitance: difference of positive and negative output (a), positive (b) and negative (c) output and sum of positive and negative output (d). The horizontal scale is 20 ns per division and the vertical scale is 300 mV per division.

Pulse width is less than 40 ns up to about 350 fC: The measured saturation behaviour for an input charge of 500 fC and 56 pF of detector capacitance is shown in Fig. 15 and is also well reproduced by simulation.

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Channel-to-channel uniformity, measured on all channels of three chips with a 36 fC delta input pulse and 56 pF detector capacitance, was 1.8% peak-to-peak for the sensitivity, 3.3% for the peaking time and 15% for the ENC. 3.4. Prototype IIIpositive input polarity preamplier, shaper, discriminator and LVDS driver Fig. 17(a) shows the input differential threshold vs. effective threshold with delta and 1=t input pulse at 56 pF detector capacitance. Due to a mistake in the design, which is corrected in the nal chip version, the discriminator output stage in this prototype was not provided with enough gain. As a consequence, the linear t of Fig. 17(a) has a non-zero offset, corresponding to a minimum detected charge. However, the slope of the linear t, 8 mV=fC and 6 mV=fC for delta and 1=t input signal, respectively, gives the correct circuit sensitivity. The value for delta input pulse is in rough agreement with the sensitivity measured with the shaper chip. The difference in slopes between the two types of input signals can be explained by ballistic decit. Fig. 17(b) shows effective threshold vs. detector capacitance for 20 mV input differential threshold for delta input pulse. The gure shows an increase of the effective threshold by a factor two between zero and 250 pF input capacitance. This increase is of the same order of magnitude of the decrease in signal amplitude, shown in Fig. 10(a) for the shaper chip. ENC vs. detector capacitance is shown in Fig. 18. A linear t gives ENC 1485e 45e Cdet pF: ENC measured with this chip is smaller (of about 20% at the largest detector capacitances) than that measured with the shaper chip. Since the two chips have the same type of preamplier and shaper, we interpret the additional noise as pick-up on the shaper chip test board. Cross-talk in the chip was less than 0.5% (the measurement method did not allow to put a lower limit). Uniformity for threshold was measured on all channels of three chips with a 36 fC delta input signal and 56 pF detector capacitance to be 30% peak to peak. The much larger non-uniformity in

Fig. 15. Measured shaper output (average of 1000 pulses) for a 500 fC; 1=t pulse input and 56 pF detector capacitance: difference of positive and negative output (a), positive (b) and negative (c) output and sum of positive and negative output (d). The horizontal scale is 20 ns per division and the vertical scale is 300 mV per division.

-50

A(mV)

-100

-150

-200

-250 0 25 50 75 100 125 150 175 200

t(ns)
Fig. 16. Measured shaper negative output pulse for cathode pad readout obtained exposing an LHCb prototype wire chamber to an 241 Am source.

Fig. 16 shows a shaper negative output pulse for cathode pad readout obtained exposing an LHCb prototype wire chamber to an 241 Am source. Pad capacitance is 50 pF: A detailed description of this chamber can be found in Ref. [1].

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100 90 Input Differential Threshold [mV] 80 Effective Threshold [fC] 70 60 50 40 30 20 10 0 0 2 4 6 8 10 12 14 16 18 20 Effective Threshold [fC] 20 18 16 14 12 10 8 6 4 2 0 0 50 100 150 200 Detector Capacitance [pF] 250

(a)

(b)

Fig. 17. (a) Input differential threshold vs. effective threshold for delta (full stars) and 1=t (full triangles) input pulses at 56 pF detector capacitance. (b) Effective threshold with delta input pulse vs. detector capacitance for 20 mV input differential threshold for the discriminator chip.

16000 14000 Equivalent noise charge[e] 12000 10000 8000 6000 4000 2000 0 0 50 100 150 200 Detector Capacitance [pF] 250 Time delay [ns]

6 5 4 3 2 1 0 -1

50

100 150 200 Input Charge [fC]

250

300

Fig. 18. Measured equivalent noise charge vs. detector capacitance for prototype III chip.

effective threshold than in shaper sensitivity can be ascribed to non-uniformity in resistance and capacitance values of the coupling stage (AC) between shaper and discriminator. We remind the reader here that the nal version of the chip will not have an AC coupling stage. Fig. 19 shows the time delay vs. input charge for the discriminator and the shaper chips with 1=t input pulse, at 56 pF detector capacitance and 20 mV differential input threshold. The similarity of the measured values with the two methods

Fig. 19. Measured time delay vs. input charge for prototype III chip (full stars) and for prototype II chip (full circles) with 1=t input pulse, at 56 pF detector capacitance and 20 mV differential input threshold.

shows that the discriminator circuit adds very little to the intrinsic time resolution due to time walk.

4. Conclusions This paper presented the design and test of three prototypes of the CARIOCA front-end chip for the LHCb muon wire chambers.

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These prototypes included positive and negative pre-amplier, differential shaper, differential discriminator and LVDS driver circuits, designed in 0:25 mm CMOS radiation tolerant technology. The measured characteristics satisfy the requirements for operation in the LHCb muon system. Good overall agreement is also observed between the measurements and PSPICE simulation results. The only missing stage is the baseline restoration circuit. This one was included in the nal prototype which was submitted to the manufacturer in November 2001.

References
[1] LHCb Collaboration, LHCb muon system, Technical Design Report, CERN/LHCC 2001-010, 2001. [2] D. Moraes, et al., CARIOCA - 0:25 mm CMOS fast binary front-end for sensor interface using a novel current-mode feedback technique, in: Proceedings of the 2001 IEEE International Symposium on Circuit and Systems, Sydney, Australia, 2001, [Vol. I], p. 360. [3] W. Bonivento, et al., Status of the CARIOCA Project, in: Proceedings of the VII Workshop on Electronics for LHC Experiments, Stockholm, Sweden, 2001, CERN 2001-005, CERN/LHCC/2001-034. [4] R.A. Boie, et al., Nucl. Instr. and Meth. 192 (1982) 365. [5] M. Newcomer, et al., Progress in development of the ASDBLR ASIC for the ATLAS TRT, in: Proceedings of the V Workshop on Electronics for LHC Experiments, Colorado, USA, 1999 CERN/LHCC/99-33. [6] C. Posch, et al., CMOS front-end for the MDT sub-detector in the ATLAS muon spectrometer, development and performance, in: Proceedings of the VII Workshop on Electronics for LHC Experiments, Stockholm, Sweden, 2001, CERN 2001-005, CERN/LHCC/2001-034.

Acknowledgements This work has been partially supported by Conselho Nacional de Desenvolvimento Cient! co i ! e Tecnologico (CNPq-Brazil) and by the European Commission (contract CT1* - CT94 - 0118). We thank A. Kashchuk of CERN for setting up the wire chamber test and for providing us with the signal injection circuits.