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Ground Bounce: (And It's Dual, V Bounce)

Ground Bounce is the noise on a 'quiet' output. Voltage with respect to ground. Ground Bounce is measured on pin with greatest noise. Worst-case pin usually furthest from ground. 256k SRAM in the 28 lead flat pack does not provide a satisfactory ground connection for operation in TTL mode for the Read conditions listed in datasheet HX6256.

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176 views

Ground Bounce: (And It's Dual, V Bounce)

Ground Bounce is the noise on a 'quiet' output. Voltage with respect to ground. Ground Bounce is measured on pin with greatest noise. Worst-case pin usually furthest from ground. 256k SRAM in the 28 lead flat pack does not provide a satisfactory ground connection for operation in TTL mode for the Read conditions listed in datasheet HX6256.

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9844352836
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Ground Bounce

(and its dual, VDD Bounce)

Concept of Ground Bounce


Quiet Device Output That Is Affected

System Input That is Affected Load Capacitance

Inductance of lead frame, bound wired, package pin, etc.

Current flow (red) during a high to low transition causing bounce. This can change the input thresholds to the device as well as result in output pulses being transmitted to a receiver.

Ground Bounce - Definition


Noise on a quiet output. Voltage with respect to ground.
Switching Outputs

High Quiet Output

VOHP VOHV VOLP VOLV

Low Quiet Output

Ground Bounce - A Closer Look

VDD Bounce

Ground Bounce - Definition


Xilinx Terminology

Ground Bounce - Measuring


Measured on pin with greatest noise. Worst-case pin usually furthest from ground. VOLP and VOLV are measured on a quiet line that is a 0; switching outputs transition from high to low for ground bounce. VOHP and VOHV are measured on a quiet line that is a 1; switching outputs transition from low to high for supply droop.

Ground Bounce - Measuring

Ground Bounce - Measuring


Worst-Case vs. Best-Case Pin

Worst-case

Best-case

Ground Bounce - Measuring


Design system and test equipment to support measurement of ground bounce
Control of patterns

When using reprogrammable devices


Special patterns can be loaded to exercise the I/O buffers and measure ground bounce.

Ground Bounce - Sample Data


ACT157 - 3 Outputs Switching

Ground Bounce - A Real Life Problem


HX6256: 256K SRAM
The 256K SRAM in the 28 lead flat pack does not provide a satisfactory ground connection for operation in TTL mode for the Read conditions listed in datasheet HX6256. The issue arises due to inadequate on-chip power bussing. Various address changes, pre-charge pulses, and switching outputs create a considerable amount of drawdown on the power bussing. Functional performance is achieved by having adequate grounding on the package (ex. Maintaining equivalent package and board grounds). The 28-lead package in correlation with the 256K SRAM has demonstrated on-chip ground bounce, which occurs when switching all addresses simultaneously; this situation could cause the device to enter into a state of oscillation. Toggling the NOE pin coincident with an address change could cause the chip to enter oscillation if all of the inputs are toggled together.

Ground Bounce: Package


Lead Inductance
14-pin plastic 68-pin plastic 68-pin PLCC Wire bonded to Solder bump to DIP DIP 8 nH 35 nH 7 nH hybrid substrate 1 nH hybrid substrate 0.1 nH

H. Johnson and M. Graham

Ground Bounce: Package


1.0 0.9 0.8

Quiet Output Noise (normalized to CDIP)

0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 LCC SOIC PDIP CDIP

Package Type

Note CDIP inductance =20 nH LCC package = 2 nH; Difference in ground bounce < 35%

National AN-640

Ground Bounce: Loading


Xilinx
Additional capacitance doesnt affect magnitude of the bounce, just duration Resonant Frequency
Minimum load, fastest outputs: 340 MHz 50 pF: 90 MHz 150 pF: 40 to 60 MHz

Agilent
Larger the capacitance, the larger the bounce

Reducing Ground Bounce


Use low slew outputs unless needed Dont group SSOs together; break them up.
Xilinx: two for each side of a ground pin

Control number of SSOs through sequencing


Example: Do address and data busses need to switch at the same time?

For some families [fill in], programming unused outputs will improve grounding or supply for output stages.

Reducing Ground Bounce


Use buffers, particularly for large memory arrays or long lines
Everything does not have to be inside of the FPGA or ASIC

Avoid sockets For spare pad locations, pre-wire power, ground, and bypass capacitor connections
haywired power and ground connections will have unneeded inductance.

Ground Bounce: Loading


Data from National Semiconductor

Quiet Outputs (National)


Data from National Semiconductor
7 Outputs Switching VDD = 5V Worst-case Pin CL = 50 pF

Reducing Ground Bounce (contd)


For SSI/MSI, center ground pins
10-15% reduction in ground bounce Higher edge rates

Reducing Ground Bounce Effects


Choose input thresholds wisely
OK, doesnt reduce ground bounce
Reduces the effects of ground bounce

TTL VIL = 0.8V Some devices offer programmable 5V CMOS or other input voltage threshold options

Keep clocks physically away from pins that can cause ground bounce Keep clocks close to ground pins

Not Obvious Situations


SSO When Using JTAG and driving board with test data over multiple parts Data pattern sensitivities, particularly with large data busses
FFFFFFFF 00000000

Test cabling, particularly for vibration, thermal/vacuum, and EMI tests. High-speed parts that are haywired in

Ground Bounce - Some Numbers


From Xilinx Application Note XAPP045
Table 3: Ground Bounce, 16 Outputs Switching, Each with 50 or 150 pF Load, VCC = 5.5V Load Slew Rate High to Low VOLP VOLV 670 1170 740 1180 480 710 330 420 Low to High VOLP VOLV 240 480 210 350 240 660 280 710

16 x 50 pF

Slow Fast Slow Fast

16 x 150 pF

Device = XC4005-5 Package = PQ208

Ground Bounce - Some Numbers


Xilinx Recommendations
Output Slew Rate The slew rate of each output buffer is, by default, reduced, to minimize power bus transients when switching non-critical signals. For critical signals, attach a FAST attribute or property to the output buffer or flip-flop. For XC4000E devices, maximum total capacitive load for simultaneous fast mode switching in the same direction is 200 pF for all package pins between each Power/Ground pin pair. For XC4000X devices, additional internal Power/Ground pin pairs are connected to special Power and Ground planes within the packages, to reduce ground bounce. Therefore, the maximum total capacitive load is 300 pF between each external Power/Ground pin pair. Maximum loading may vary for the low-voltage devices. For slew-rate limited outputs this total is two times larger for each device type: 400 pF for XC4000E devices and 600 pF for XC4000X devices. This maximum capacitive load should not be exceeded, as it can result in ground bounce of greater than 1.5 V amplitude and more than 5 ns duration. This level of ground bounce may cause undesired transient behavior on an output, or in the internal logic. This restriction is common to all high-speed digital ICs, and is not particular to Xilinx or the XC4000 Series.

Ground Bounce - Some Numbers


Actel Recommendation
Device A1010A/A1020A A1010A/1020A A1020A A1010A/1020A A1010A/A1020A A1280/A1280XL A1240/A1240XL A1240/A1225/A1225XL A1225/A1225XL A1400 Family A1400 Family Package 44 68 84 84 100 PLCC PLCC PLCC PGA PQFP 20 pf 40 60 80 80 80 160 120 80 80 64 128 35 pf 22 34 45 45 45 90 68 45 45 48 64 50 pf 16 24 32 32 32 64 48 32 32 42 58

PG 176, PQ 160 PG 132, PQ 144 84 PLCC 100 PGA, PQFP 84 PLCC Other packages

Notes: 1. Double SSO value for low slew drivers in Act 3 family. 2. Signals are simultaneously switching if transition within 10 ns 3. Signals are adjacent; can increase if drivers separated 4. Criteria: 1.5V pulse, 2 ns.

Related Issues
Propagation Delay Dynamic Thresholds

Propagation Delay Affects


1 Output Switching

Clock 8 Outputs Switching

Affects on Input Thresholds


Ground Reference Shifts

Affects on Input Thresholds


Terms and Specifications (National)

VIHD

The minimum HIGH input level such that normal switching/functional characteristics are observed during output transients. The maximum LOW input level such that normal switching/functional characteristics are observed during output transients.

VILD

Affects on Input Thresholds


54ACQ244 @ VCC = 4.5V, T = 25 C

VIH VIHD VIL VILD

Typ 2.25 3.1 2.25 1.9

Worst-Case 3.15 3.5 1.35 1.5

References
FACT Advanced CMOS Logic Databook, 1990 Edition Understanding and Minimizing Ground Bounce, Application Note AN-640, National Semiconductor Dynamic Threshold for Advanced CMOS Logic, Application Note AN-680, R. Mentzer, National Semiconductor. Simultaneously Switching Output Limits for Actel FPGAs, Actel Corp., April 1996 High-Speed Digital Design: A Handbook of Black Magic, Howard W. Johnson and Martin Graham, 1993 Ground Bounce Basics and Best Practices, P. King, Agilent Technologies.

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