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Ee457 Unix Modelsim Setup and Testing

The document provides instructions for setting up a Unix account to use ModelSim for verilog simulation and testing. It details how to: 1) Execute a setup script to configure the ModelSim environment and add setup lines to the .login file. 2) Create a test project directory and source files for a middle finder circuit example. 3) Invoke ModelSim in a VNC or Xwin32 window to compile and simulate the example design.

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Chhavi Mittal
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128 views

Ee457 Unix Modelsim Setup and Testing

The document provides instructions for setting up a Unix account to use ModelSim for verilog simulation and testing. It details how to: 1) Execute a setup script to configure the ModelSim environment and add setup lines to the .login file. 2) Create a test project directory and source files for a middle finder circuit example. 3) Invoke ModelSim in a VNC or Xwin32 window to compile and simulate the example design.

Uploaded by

Chhavi Mittal
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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8/13/2009, 3/13/2011 EE457 Instructions to setup unix account for modelsim and testing =========================================== To setup your unix

account to use modelsim, do the following. 1. login to your unix account. 2. from your home directory, execute (just type in and return the following command at your unix prompt) ~eeview/msim.setup 3. The response will be as shown below: nunki-ee457lab{15} ~eeview/msim.setup tar: blocksize = 6 x modelsim, 0 bytes, 0 tape blocks x modelsim/modelsim.env.setup, 570 bytes, 2 tape blocks 4. Basically we create a modelsim directory under your home directory if you do not have a modelsim directory from previous setups. We also add the following lines to your .login file: #################################################################### # The following lines are added in order to provide access to the # # ModelSim VHDL/Verilog simulation tools used in # # EE201L/EE457/EE560. # #################################################################### ### setup environment for ModelSim VHDL/Verilog Simulation tools if (-e ~eeview/modelsim.setup) then source ~eeview/modelsim.setup else echo "**WARNING** ModelSim environment not properly set-up" endif #### 5. Now to execute the newly added lines in the .login file, either logout and login, or do the following command: source .login 6. modelsim subdirectory is created for you so that you can place all modelsim projects under this subdirectory. If there is a modelsim subdirectory already, we will not overwrite it! 7. Now create a test project by creating a subdirectory under the modelsim directory: cd cd modelsim mkdir middle_finder cd middle_finder ~ee457lab/middle_finder.shar 8. The above causes bringing of the following files into your middle_finder subdirectory. middle_finder.v middle_finder_tb.v middle_finder_tb_exhaustive_self_verifying.v middle_finder_tb_exhaustive_self_verifying_solution.v 9. Invoke modelsim using vsim command in a vncviewer window or a Xwin32 window. Note that the modelsim uses a GUI and you need to use either vncviewer window or Xwin32 window so that you can display the graphical windows. Start a new project with project location same as your ~/modelsim/middle_finder. Addd to the project, the four verilog files. Compile only the following two: middle_finder.v, middle_finder_tb_exhaustive_self_verifying_solution.v

Simulate the testbench module middle_finder_tb When you invoke simulation, in the start simulation dialog box, unselect "Enable optimization" box. Otherwise, it does not show any signals to watch in the waveform.

If you are new to vncviewer, please download the vncviewer on to your home PC and connect to the university SUN (aludra/nunki/girtab) using the following: http://www-scf.usc.edu/~eeview/README.vnc.setup.pdf Free VNC Viewer is available for download from the following website for PC (x86 windows machine) only. http://www.realvnc.com/products/download.html
10. Now you can follow the EE201L tutorial on Modelsim. Though this tutorial is written for ModelSim MXE on a PC, most of it is useful for any modelsim http://www-classes.usc.edu/engr/ees/457/ee457_Verilog/ModelSim_Testing_USC.pdf 11. In most of your assignments, your instructor may provide you a .do file. It is a batch file to automate the various tasks (after setting up the project and adding the source files to the project) such as compiling the verilog files, starting the simulation, adding signals to the waveform, changing radix, running the simulation, adding a cursor, etc. For example, one can write a .do file for the current design as follows: # middle_finder.do vlib work vlog +acc "middle_finder.v" vlog +acc "middle_finder_tb.v" vsim -lib work -t 1ps -novopt work.middle_finder_tb view structure view signals view wave do middle_finder_wave.do log -r * run 30ns WaveRestoreZoom {0 ns} {30 ns} # quit -sim Notice that tha above .do file is invoking another .do file middle_finder_wave.do, which adds the needed signals and sets up radices. Invoke the .do file at the ModelSim> prompt by typing do middle_finder.do Note that unless you have setup your project directory same as the directory where you have all the verilog files and .do files the above does not work properly. 12. Enjoy simulating and proving your designs using modelsim.

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