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Advance Power Electronics

Overlap in Rectifiers
LECTURE-8 LECTURE-

Dr. Tahir Izhar

Overlap
Introduction
The overlap is the effect of source impedance on rectifier characteristics. h t i ti The three pulse, or half wave three phase rectifier is considered here to explain the effect. It is not a practical circuit, but convenient to use it as a vehicle to explain the overlap . First the ideal behavior of this circuit is reviewed then the source impedance is included to investigate the overlap. If the load inductance is assumed to be infinite, the load current will be constant. If the source impedance is ignored, the current can commutate instantaneously form one diode to the next.

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Overlap
Introduction
The diode with the highest anode voltage will conduct at any instant i ti i t t in time, th th the three di d conduct f 120O each. diodes d t for h The load current is constant and contributed by each diode of 120O duration. The current in three phases starts and stops instantaneously. In practice, time is required for the currents to change due to p q g supply side source impedance. The major contributor of this impedance is leakage inductances of the transformer. The main reason for the unpopularity of the half bridge is that it draws DC current components form the mains which may lead to cause saturation in distribution transformer.

Ideal 3-Pulse Converter 3-

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Ideal 3-Pulse Converter 3The current through Ld is continuous, made up of the contributions from each diode of 120O duration. For the ideal case the currents can start and stop instantaneously. In practice, time is required for the current change to take place due to the supply source inductance. The major contributor to the supply inductance is the transformer leakage inductance.

Effect of Source Impedance

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Effect of Source Impedance

Effect of Source Impedance

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Overlap Analysis
Consider commutation from DR to DY which will be initiated as VYN exceeds VRN. at time t0. This is the time when line voltage, VYR is passing through zero to become positive. To analyze the commutation events, the equivalent circuit is shown below.

Overlap Analysis
The voltage VYR drives the circulating current, iC in the direction shown. When iC reaches the value Id, iR will become zero and DR is extinguished and iY has become equal to Id and has taken over the conduction. The period when both diodes are conducting is called the overlap. It should be noted that

iR + iY = I d
diR di = Y dt dt

(1)

(2)

The equation governing the equivalent Circuit with assumed sign convention is

vYR = 2 LS

diC dt

(3)

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Overlap Analysis
LS diC vYR = dt 2
(4) Consequently vYR is responsible for supplying the volt-seconds which change the q y p pp y g g current in LS. Furthermore during the overlap time the output voltage, vo of the rectifier is:

vo = vYN

vYR 2

Where vYR /2 is the inductance LS drop as can be seen from the equivalent circuit during overlap.

v v vo = vYN YN RN 2 2 vYN vRN vo = vYN + 2 2 1 vo = (vRN + vYN ) 2

(5)

Overlap Analysis
Hence vo is the instantaneous average of the red and yellow phase voltages as y phase shown above and not the yellow p voltage for the ideal case when LS=0. Thus for the period up until t0, the output voltage vo has been equal to vRN. From t0 onwards vo becomes 1/2(vRN+vYN) until conduction has been transferred from red to yellow phase. After conduction transfer, vo will become vYN as before. Analytical A l i l expressions f the i for h instantaneous phase currents during overlap can be derived from equation (4) because iY=iC during this time. iY is initially zero, and rises according to iC when overlap starts.

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Overlap Analysis
iY = 1 vYR dt 2 LS 0
t

(6)

From equation (4) it can be seen that as t=0 at t0

iYR = 3vRN sin t

(7) (8)

As from equation (1)

iR + iY = I d iR = I d iY iR = I d 3vRN (1 cos t ) 2LS

Equation (8) and (9) define the instantaneous currents during the overlap time

Overlap Analysis
These sinusoidal transitions replace the instantaneous switching from one diode to another that take place with zero source impedance. p g p The shape of vo is shown in the diagram. It follow VRN up to t0, then follow (vRN+vYN) during overlap and then recovered to vYN when t=T. The duration of the overlap can be derived from equation (8), because overlap finishes when iY=Id Hence

Id =
Therefore

3vRN (1 cos T ) 2LS

T=

2LS I d cos 1 1 3vRN 1

(10)

Equation (10) is not a simple expression, but nevertheless allows T to be calculated. The average output voltage, Vd is reduced because of the volt-second shown shaded in the figure.

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Overlap Analysis
That volt-second is absorbed voltacross the source impedance each time current commutates from one phase to another. The output voltage reduction due to overlap can be estimated form the waveform shown.
Vd = Vd VT
(11)

Where Vd is actual voltage, Vd is ideal voltage and VT is the loss of voltage due to overlap.

Overlap Analysis
The volt-seconds needed to change the current in the yellow phase inductance LS , from 0 to Id is clearly LSId. Hence

VT =

3LS I d T

(12)

Where the factor 3 is included because there are three overlap events in each period of Mains cycle, T.

T= VT =

1 2 = f

(13)

3LS Id 2

(14)

Finally, putting values in equation (4) gives

Vd =

3 3 3LS vRN Id 2 2

(15)

Equation (15) suggest an equivalent circuit as shown

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Overlap Analysis
The half bridge rectifier is viewed as a DC source of value

Vd =

3 3 vRN 2

(16)

With in internal source resistance of

RC =

3LS 2

(17)

It should be noted that there is not loss associated with RC. This model only applies when the overlap condition prevails.

Summary
In this lecture, the effect of source impedance on the performance of the rectifier circuit is investigated. The inductive reactance of the ac supply is normally much greater than its resistance. Due to the source inductance, time is required to change the current resulting a delay in current commutation. Three pulse half bridge circuit with source inductance is used to explain the phenomenon of overlap overlap. Once the overlap phenomenon is understood, it can be applied to other practical converter circuits.

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Thank you
For your attention

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