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ASIC Layout - 2 Standard Cell Flow

The document describes the standard cell ASIC design flow using Mentor Graphics tools. It involves generating a component-level netlist from Verilog, placing and routing standard cells using floorplanning and layout tools like IC Station, performing design rule checking and layout vs schematic checks with Calibre, and generating mask data for fabrication. Key steps include creating a standard cell block in IC Station, auto-floorplanning the block, auto-placing cells and ports, auto-routing nets, and fixing any errors found in DRC.

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193 views

ASIC Layout - 2 Standard Cell Flow

The document describes the standard cell ASIC design flow using Mentor Graphics tools. It involves generating a component-level netlist from Verilog, placing and routing standard cells using floorplanning and layout tools like IC Station, performing design rule checking and layout vs schematic checks with Calibre, and generating mask data for fabrication. Key steps include creating a standard cell block in IC Station, auto-floorplanning the block, auto-placing cells and ports, auto-routing nets, and fixing any errors found in DRC.

Uploaded by

diva9jobs
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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ASIC Physical Design Standard-Cell Design Flow

Course Web Page Reference: Designing Standard Cells ASICs with the ASIC Design Kit (ADK) and Mentor Graphics Tools

(can also do full custom layout)

ASIC Physical Design (Standard Cell)


Component-Level Netlist (EDDM format)

Std. Cell Layouts Libraries

Floorplan Chip/Block ICblocks

Mentor Graphics IC Station


(adk_ic)

Process Data Design Rules

Place & Route Std. Cells

Generate Mask Data

Design Rule Check Calibre

Backannotate Schematic Calibre

Layout vs. Schematic Check Calibre

IC Mask Data

Mach TA/Eldo Simulation Model

Mentor Graphics Analog/Mixed-Signal IC Design Flow

ASIC CAD tools available in ECE


Modeling and Simulation Questa ADMS = Questa+Modelsim+Eldo+ADiT (Mentor Graphics) Verilog-XL, NC_Verilog, Spectre (Cadence) Design Synthesis (digital) Leonardo Spectrum (Mentor Graphics) Design Compiler (Synopsys), RTL Compiler (Cadence) Design for Test and Automatic Test Pattern Generation Tessent DFT Advisor, Fastscan, SoCScan (Mentor Graphics) Schematic Capture & Design Integration Design Architect-IC (Mentor Graphics) Design Framework II (DFII) - Composer (Cadence) Physical Layout IC Station (Mentor Graphics) SOC Encounter, Virtuoso (Cadence) Design Verification Calibre DRC, LVS, PEX (Mentor Graphics) Diva, Assura (Cadence)

Mentor Graphics ASIC Design Kit (ADK)


We also have ADKs for Cadence tools for several technologies

Technology files & standard cell libraries AMI: ami12, ami05 (1.2, 0.5 m) TSMC: tsmc035, tsmc025, tsmc018 (0.35, 0.25**, 0.18 m) **also have VT Cadence lib Current MOSIS Instructional: IBM 180nm CMOS (7RF), ON Semi 0.5um CMOS Current MOSIS Unfunded Research: IBM 130nm CMOS (8RF), 130nm SiGE BiCMOS(8HP) IC flow & DFT tool support files: Simulation models

Standard cell synthesis libraries (LeonardoSpectrum) Design for test & ATPG libraries (DFT Advisor, Fastscan) Schematic capture (Design Architect-IC) IC physical design (standard cell & custom)

VHDL/Verilog/Mixed-Signal models (Modelsim SE/Questa ADMS) Analog (SPICE) models (Eldo, ADiT) *Post-layout timing (Mach TA) * obsolete: Mach TA replaced by ADiT *Digital schematic (Quicksim II, Quicksim Pro) * obsolete: HDL or Eldo now used

Standard cell models, symbols, layouts (IC Station) Design rule check, layout vs schematic, parameter extraction (Calibre)

Automated ASIC Design Flow


Source: CMOS IC Layout, Dan Clein

Std Cell ASIC

Full Custom IC

IC Station full-custom design flow

Cell-Based IC

I/O pads

Cell-Based Block

Basic standard Cell layout

Source: Weste CMOS VLSI Design

Automated Layout Design Flow in IC Station


Import netlist into IC Station Floorplan block or chip Place std cells Place I/O ports

Route cell interconnects

Remove space

DRC, LVS, PEX fix errors

Preparation for Layout


1.

Use Design Architect-IC to convert Verilog netlist to Mentor Graphics EDDM netlist format
Invoke Design Architect-IC (adk_daic) On menu bar, select File > ImportVerilog

2.

Open the generated schematic for viewing

Netlist file: count4.v (theVerilog netlist) Output directory: count4 (for the EDDM netlist) Mapping file $ADK/technology/adk_map.vmp

3.

Create design viewpoints for ICstation tools


adk_dve count4 t tsmc035

Click Schematic in DA-IC palette Select schematic in directory named above (see next slide) Click Update LVS in the schematic palette to create a netlist to be used later by Calibre (V.Ps: layout, lvs, sdl, tsmc035)

Can also create gate/transistor schematics directly in DA-IC using components from the ADK library

DA-IC generated schematic

Create a std-cell based logic block in IC Station


Invoke: adk_ic In IC Station palette, select: Create Cell Cell name: count4 Attach library: $ADK/technology/ic/process/tsmc035 Process: $ADK/technology/ic/process/tsmc035 Rules file: $ADK/technology/ic/process/tsmc035.rules Angle mode: 45 Cell type: block Select With connectivity EDDM schematic viewpoint: count4/layout Logic loading options: flat

Create Cell dialog box

Floorplanning (Text chap. 15, 16)


Floorplanning: arrange major blocks prior to detailed layout

to minimize chip area

input is a netlist of circuit blocks (hierarchical) estimate layout areas, shapes, etc. do initial placement of blocks (keep highly-connected blocks

close) decide location of I/O pads, power, clock

Autofloorplan options
Aspect ratio defines block shape Max dimensions #Rows specify or automatic Edge gaps between core & external rows (for pins, etc.) Route area ratio vertical space between rows Internal row layout can flip bottom

Auto-floorplan the block with ICplan


place & route > autofp

cell rows

cell boundary

Auto-place the std cells


Autoplc > StdCel

Auto-place ports (signal connections on cell boundaries)


Autoplc > Ports

AutoRoute all nets (hand-route unrouted overflows)


Then: Add > Port Text to copy port names from schematic for Calibre

16 by 8 divider circuit

Layout design rule check (DRC)


Technology-specific design rules specify minimum sizes,

spacing, etc. of features to ensure reliable fabrication


Design rules file specified at startup

Ex. tsmc035.rules
From main palette, select ICrules
Click Check and then OK in prompt box

(can optionally select a specific area to check) Rules checked in numeric order

Common errors detected by DRC


To fix, click on First in palette to highlight first error Error is highlighted in the layout Click View to zoom in to the error (see next) Example: DRC9_2: Metal2 spacing = 3L Fix by drawing a rectangle of metal2 to fill in the gap between contacts that should be connected Click Next to go to next error, until all are fixed

NOTE: The layout must be free of DRC errors if MOSIS is to fabricate the chip; they will run their own DRC.

Sample error: DRC9_2 metal2 spacing = 3L

Draw rectangle of metal2 to fill gap

It also called contact-to-contact metal 2 spacing DRC9_2 error

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