Chapter 11: Basic I/O Interface - Part 2

113 THE PROGRAMMABLE PERIPHERAL

82C55 programmable peripheral interface (PPI) is a popular, low-cost interface component found in many applications. The PPI has 24 pins for I/O, programmable in groups of 12 pins and groups that operate in three distinct modes of operation. 82C55 can interface any TTL-compatible I/O device to the microprocessor.
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 The 82C55 (CMOS version) requires wait states if operated with a processor using higher than an 8 MHz clock.
also provides at least 2.5 mA of sink (logic 0) current at each output, a maximum of 4.0 mA

Because I/O devices are inherently slow, wait states used during I/O transfers do not impact significantly upon the speed of the system. The 82C55 still finds application even in the latest Core2-based computer system.

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 82C55 is used for interface to the keyboard and parallel printer port in many PCs.
found as a function within an interfacing chip set also controls the timer and reads data from the keyboard interface

An experimentation board is available that plugs into the parallel port of a PC, to allow access to an 8255 located on the board. The 8255 is programmed in either assembly language or Visual C++ through drivers available with the board.
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Basic Description of the 82C55

Fig 1118 shows pin-outs of the 82C55 in DIP and surface mount (flat pack) format. The three I/O ports (labeled A, B, and C) are programmed as groups.
group A connections consist of port A (PA7PA0) and the upper half of port C (PC7PC4) group B consists of port B (PB7PB0) and the lower half of port C (PC3PC0)

82C55 is selected by its CS pin for programming and reading/writing to a port.

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Figure 1118 The pin-out of the 82C55 peripheral interface adapter (PPI).

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 Table 112 shows I/O port assignments used for programming and access to the I/O ports. In the PC, a pair of 82C55s, or equivalents, are decoded at I/O ports 60H63H and also at ports 378H37BH. The 82C55 is a fairly simple device to interface to the microprocessor and program. For 82C55 to be read or written, the CS input must be logic 0 and the correct I/O address must be applied to the A1 and A0 pins. Remaining port address pins are dont cares.
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 Fig 1119 shows an 82C55 connected to the 80386SX so it functions at 8-bit addresses C0H (port A), C2H (port B), C4H (port C), and C6H (command register).
this interface uses the low bank of the I/O map

All 82C55 pins are direct connections to the 80386SX, except the CS pin. The pin is decoded/selected by a 74ALS138 decoder. A RESET to 82C55 sets up all ports as simple input ports using mode 0 operation.
initializes the device when the processor is reset
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Figure 1119 The 82C55 interfaced to the low bank of the 80386SX microprocessor.

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 After a RESET, no other commands are needed, as long as it is used as an input device for all three ports. 82C55 is interfaced to the PC at port addresses 60H63H for keyboard control.
also for controlling the speaker, timer, and other internal devices such as memory expansion

It is also used for the parallel printer port at I/O ports 378H37BH.

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Programming the 82C55

82C55 is programmed through two internal command registers shown in Figure 1120. Bit position 7 selects either command byte A or command byte B.
command byte A programs functions of group A and B byte B sets (1) or resets (0) bits of port C only if the 82C55 is programmed in mode 1 or 2

Group B (port B and the lower part of port C) are programmed as input or output pins.
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Figure 1120 The command byte of the command register in the 82C55. (a) Programs ports A, B, and C. (b) Sets or resets the bit indicated in the select a bit field.

group B operates in mode 0 or mode 1 mode 0 is basic input/output mode that allows the pins of group B to be programmed as simple input and latched output connections Mode 1 operation is the strobed operation for group B connections data are transferred through port B handshaking signals are provided by port C
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 Group A (port A and the upper part of port C) are programmed as input or output pins. Group A can operate in modes 0, 1, and 2.
mode 2 operation is a bidirectional mode of operation for port A

If a 0 is placed in bit position 7 of the command byte, command byte B is selected This allows any bit of port C to be set (1) or reset (0), if the 82C55 is operated in either mode 1 or 2.
otherwise, this byte is not used for programming
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Mode 0 Operation
Mode 0 operation causes 82C55 to function:
as a buffered input device as a latched output device

Fig 1121 shows 82C55 connected to a set of eight seven-segment LED displays. These are standard LEDs.
the interface can be modified with a change in resistor values for an organic LED (OLED) display or high-brightness LEDs
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Figure 1121 An 8-digit LED display interfaced to the 8088 microprocessor through an 82C55 PIA.

ports A & B are programmed as (mode 0) simple latched output ports port A provides segment data inputs port B provides a means of selecting one display position at a time for multiplexing the displays the 82C55 is interfaced to an 8088 through a PLD so it functions at I/O port numbers 0700H0703H PLD decodes the I/O address and develops the write strobe for the WR pin of the 82C55
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 Resistor values in Fig 1121 are chosen so the segment current is 80 mA.
required to produce average 10 mA current per segment as the displays are multiplexed

A six-digit display uses a segment current of 60 mA for an average of 10 mA per segment. Peak anode current in an eight-digit display is 560 mA (seven segments 80 mA).
average anode current is 80 mA

In a six-digit display, peak current would be 420 mA (seven segments 60 mA).

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 In this display, the segment load resistor passes 80 mA current and has approximately 3.0 V across it. The value of the resistor is 3.0 V 180 mA = 37.5 Ohm. The closest standard resistor value of 39 Ohm is used in Fig1121. Programming the 82C55 is accomplished by the short sequence of instructions listed in Example 119. Ports A and B are programmed as outputs.
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An LCD Display Interfaced to the 82C55

LCDs (liquid crystal displays) have replaced LED displays in many applications. Fig 1122 shows an Optrex DMC-20481 LCD display interfaced to an 82C55.
DMC-20481 is a 4-line by 20-characters-per-line display that accepts ASCII code as input data

It also accepts commands that initialize it and control its application.

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Figure 1122 The DMC-20481 LCD display interfaced to the 82C55.

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 The data connections, which are attached to the 82C55 port A, are used to input display data and to read information from the display. For a 4-bit interface, D4D7 pins are used where the data must be formatted with the high nibble first, followed by the low nibble. A few newer OLED devices contain a serial interface that uses a single pin for the data.

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 To program DMC-20481 it must first be initialized. This applies to any display using the HD44780 (Hitachi) display driver IC. The entire line of small display panels from Optrex and most other manufacturers is programmed in the same manner. To program DMC-20481 it must first be initialized.
this applies to any display using the HD44780 (Hitachi) display driver integrated circuit
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 Initialization is accomplished via the following:

1. Wait at least 15 ms after VCC rises to 5.0 V 2. Output the function set command (30H), and wait at least 4.1 ms 3. Output the function set command (30H) a second time, and wait at least 100 s 4. Output the function set command (30H) a third time, and wait at least 40 s 5. Output the function set command (38H) a fourth time, and wait at least 40 s 6. Output 08H to disable the display, and wait at least 40 s
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 7. Output a 01H to home the cursor and clear the display, and wait at least 1.64 ms 8. Output the enable display cursor off (0CH), and wait at least 40 s 9. Output 06H to select auto-increment, shift the cursor, and wait at least 40 s

Software to accomplish the initialization of the LCD display is listed in Example 1112. The time delays can also be obtained by using a timer in C++.

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 After initialization, time delays are no longer needed when sending data or many commands to the display. The clear display command still needs a time delay as the busy flag is not used . Instead of a time delay, the busy flag is tested to see whether the display has completed an operation. The BUSY procedure tests the LCD display and only returns when the display has completed a prior instruction.
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 Once the BUSY procedure is available, data can be sent to the display by writing another procedure called WRITE. The WRITE procedure uses BUSY to test before trying to write new data to the display. Example 1114 shows the WRITE procedure, which transfers the ASCII character from the BL register to the current cursor position of the display.

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 The only other procedure needed for a basic display is the clear & home cursor procedure, called CLS, shown in Example 1115. This procedure uses the SEND macro from the initialization software to send the clear command to the display. With CLS and the procedures presented thus far, you can display any message on the display, clear it, display another message, and basically operate the display.
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A Stepper Motor Interfaced to the 82C55.

Another device often interfaced to a computer system is the stepper motor.
a digital motor because it is moved in discrete steps as it traverses through 360

An inexpensive stepper motor is geared to move perhaps 15 per step A more costly, high-precision stepper motor can be geared to 1 per step.
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 In all cases, these steps are gained through many magnetic poles and/or gearing. Figure 1123 shows a four-coil stepper motor that uses an armature with a single pole.
two coils are energized

If less power is required, one coil may be energized at a time, causing the motor to step at 45, 135, 225, and 315. The motor is shown with the armature rotated to four discrete places, called full stepping.
accomplished by energizing the coils, as shown
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Figure 1123 The stepper motor showing full-step operation: (a) 45 (b) 135 (c) 225 (d) 315.

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 The motor is driven by NPN Darlington amp pairs to provide a large current to each coil. A circuit that can drive this stepper motor is illustrated in Fig 1124.
with the four coils shown in place

This circuit uses the 82C55 to provide drive signals used to rotate the motor armature in either the right- or left-hand direction. A simple procedure that drives the motor is listed in Example 1116 in both assembly language and as a function in C++.
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Figure 1124 A stepper motor interfaced to the 82C55. This illustration does not show the decoder.

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Key Matrix Interface

Keyboards come in a variety of sizes, from standard 101-key QWERTY keyboards to special keyboards that contain 4 to 16 keys. Fig 1125 is a key matrix with 16 switches interfaced to ports A and B of an 82C55.
the switches are formed into a 4 4 matrix, but any matrix could be used, such as a 2 8

The keys are organized into four rows and columns: (ROW0ROW3) (COL0COL3)
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Figure 1125 A 4 4 keyboard matrix connected to an 8088 microprocessor through the 82C55 PIA.

the 82C55 is decoded at I/O ports 50H53H for an 8088 port A is programmed as an input port to read the rows port B is programmed as an output port to select a column a flowchart of the software required to read a key from the keyboard matrix and debounce the key is illustrated in Fig 1126
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Figure 1126 The flowchart of a keyboard-scanning procedure.

keys must be debounced, normally with a time delay of 1020 ms the software uses a procedure called SCAN to scan the keys and another called DELAY10 to waste 10 ms of time for debouncing the main keyboard procedure is called KEY and appears in Example 1117 the KEY procedure is generic, and can handle any configuration from a 1 1 matrix to an 8 8 matrix.
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 The ShortDelay procedure is needed as the computer changes port B at a very high rate .
the time delay allows the data sent to port B to settle to their final state

This is not needed if scan rate (time between output instructions) does not exceed 30 KHz.
if the scanning frequency is higher, the device generates radio interference

If so, the FCC will not approve application in any accepted system
without certification the system cannot be sold
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Mode 1 Strobed Input

Causes port A and/or port B to function as latching input devices.
allows external data to be stored to the port until the microprocessor is ready to retrieve it

Port C is used in mode 1 operationnot for data, but for control or handshaking signals.
to help operate either or both port A and B as strobed input ports

Fig 1127 shows how both ports are structured for mode 1 strobed input operation.
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Figure 1127 Strobed input operation (mode 1) of the 82C55. (a) Internal structure and (b) timing diagram.

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Signal Definitions for Mode 1 Strobed Input

STB
The strobe input loads data to the port latch, which holds the information until it is input to the microprocessor via the IN instruction.

IBF
Input buffer full is an output indicating that the input latch contains information.
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INTR
Interrupt request is an output that requests an interrupt. The INTR pin becomes a logic 1 when STB returns to a logic 1. Cleared when data are input from the port by the processor.

INTE
Interrupt enable signal is neither input nor output; it is an internal bit programmed via port PC4 (port A) or PC2 (port B) bit position.
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PC7, PC6
The port C pins 7 and 6 are general-purpose I/O pins that are available for any purpose.

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Strobed Input Example

An example of a strobed input device is a keyboard. The keyboard encoder debounces the key switches and provides a strobe signal whenever a key is depressed.
the data output contains ASCII-coded key code

Figure 1128 illustrates a keyboard connected to strobed input port A.

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Figure 1128 Using the 82C55 for strobed input operation of a keyboard.

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Mode 1 Strobed Output

Fig 1129 shows the internal configuration and timing diagram of 82C55 when operated as a strobed output device under mode 1. Strobed output operation is similar to mode 0 output operation.
except control signals are included to provide handshaking

When data are written to a strobed output port, the output buffer full signal becomes logic 0 to indicate data are present in the port latch.
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Figure 1129 Strobed output operation (mode 1) of the 82C55. (a) Internal structure and (b) timing diagram.

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Signal Definitions for Mode 1 Strobed Output

OBF
Output buffer full goes low whenever data are output (OUT) to the port A or B latch. The signal is set to logic 1 when the ACK pulse returns from the external device.

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ACK
The acknowledge signal causes the OBF pin to return to logic 1. The ACK signal is a response from an external device, indicating that it has received data from the 82C55 port.

INTR
Interrupt request often interrupts the processor when the external device receives the data via the ACK signal. Qualified by the internal INTE (interrupt enable) bit.
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INTE
Interrupt enable is neither input nor output; it is an internal bit programmed to enable or disable the INTR pin. INTE A is programmed using PC6 bit. INTE B is programmed using the PC2 bit.

PC4, PC5
Port C pins PC4 and PC5 are general-purpose I/O pins. The bit set and reset command is used to set or reset these two pins.
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Strobed Output Example

The printer interface demonstrates how to achieve strobed output synchronization between the printer and the 82C55. Figure 1130 illustrates port B connected to a parallel printer, with eight data inputs for receiving ASCII-coded data, a DS (data strobe) input to strobe data into the printer, and an ACK output to acknowledge the receipt of the ASCII character.
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Figure 1130 The 82C55 connected to a parallel printer interface that illustrates the strobed output mode of operation for the 82C55.

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Mode 2 Bidirectional Operation

Mode 2 is allowed with group A only. Port A becomes bidirectional, allowing data transmit/receive over the same eight wires.
useful when interfacing two computers

Also used for IEEE-488 parallel high-speed GPIB (general- purpose instrumentation bus) interface standard. Figure 1131 shows internal structure and timing for mode 2 bidirectional operation.
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Figure 1131 Mode 2 operation of the 82C55. (a) Internal structure and (b) timing diagram.

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Signal Definitions for Bidirectional Mode 2 INTR

Interrupt request is an output used to interrupt the microprocessor for input and output conditions.

OBF
Output buffer full is an output indicating the output buffer contains data for the bidirectional bus.
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ACK
Acknowledge is an input that enables the three-state buffers so that data can appear on port A. If ACK is logic 1, the output buffers of port A are at their high-impedance state.

STB
The strobe input loads the port A input latch with external data from the bidirectional port A bus.
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PC0, PC1, and PC2

These pins are general-purpose I/O pins in mode 2 controlled by the bit set and reset command.

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IBF
Input buffer full is an output used to signal that the input buffer contains data for the external bidirectional bus.

INTE
Interrupt enable are internal bits (INTE1 & INTE2) that enable the INTR pin. The state of the INTR pin is controlled through port C bits PC6 (INTE1) and PC4 (INTE2).
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The Bidirectional Bus

The bidirectional bus is used by referencing port A with the IN and OUT instructions. To transmit data through the bidirectional bus, the program first tests to determine whether the output buffer is empty.
if so, data are sent to the output buffer via OUT

The external circuitry also monitors the signal to decide whether the microprocessor has sent data to the bus.
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 To receive data through the bidirectional port A bus, IBF is tested with software to decide whether data have been strobed into the port.
if IBF = 1, data is input using IN

The external interface sends data to the port by using the STB signal.
the IBF signal becomes logic 1 and data at port A are held inside the port in a latch

When the IN executes, the IBF bit is cleared and data in the port are moved into AL. See Example 1121 for a procedure.
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 The INTR (interrupt request) pin can be activated from both directions of data flow through the bus. If INTR is enabled by both INTE bits, the output and input buffers both cause interrupt requests. This occurs when data are strobed into the buffer using STB or when data are written using OUT.

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82C55 Mode Summary

Figure 1132 shows a graphical summary of the three modes of operation for the 82C55. Mode 0 provides simple I/O. Mode 1 provides strobed I/O. Mode 2 provides bidirectional I/O. These modes are selected through the command register of the 82C55.

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Figure 1132 A summary of the port connections for the 82C55 PIA.

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The Serial EEPROM Interface

In Chapter 10, Figure 1023, a serial EEPROM is illustrated, but at that point in the text, no I/O existed for an interface. Suppose that port C of an 82C55 is used for connection to this interface and software is needed to drive the interface. The PC0 pin is programmed as an output to send data and as an input to receive data from the EEPROM.
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Chapter 10, Figure 1023 A serial EEPROM interface.

this memory interface has two signal lines one is a serial clock (SCL); the other a bidirectional serial data line (SDA) not meant to replace system main memory it is fast enough for music or other low-speed data

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 Refer to Figure 1024. The data format for the software for reading and writing data to the EEPROM is also illustrated in Example 1122. This software is written in C with some assembly language, but it can also be developed in assembly language. I/O port address for the command register is 0x1203, and 0x1202 for the port C register.
the time delay should be 1.25 s for a data rate of 400 KHz
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Chapter 10, Figure 1024 Data signals to the serial EEPROM for a read or a write.

the serial data contains the address in the first byte as well as a device code of 1010, which represents the EEPROM other serial devices have different device codes this is followed by the memory location and the data in additional bytes

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114 8254 PROGRAMMABLE INTERVAL TIMER

The 8254 consists of three independent 16-bit programmable counters (timers). Each counter is capable of counting in binary or binary-coded decimal (BCD).
maximum allowable input frequency to any counter is 10 MHz

Useful where the microprocessor must control real-time events.

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 Usage includes real-time clocks, event counters, and motor speed/direction control. Timer appears in the PC decoded at ports 40H43H to do the following:
1. Generate a basic timer interrupt that occurs at approximately 18.2 Hz 2. Cause the DRAM memory system to be refreshed 3. Provide a timing source to the internal speaker and other devices.

Timer in the PC is an 8253 instead of 8254.

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8254 Functional Description

Figure 1133 shows the pin-out of the 8254, a higher-speed version of the 8253, and a diagram of one of the three counters. Each timer contains:
a CLK input which provides the basic operating frequency to the timer a gate input pin which controls the timer in some modes an output (OUT) connection to obtain the output of the timer
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Figure 1133 The 8254 programmable interval timer. (a) Internal structure and (b) pin-out. (Courtesy of Intel Corporation.)

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 The signals that connect to the processor are the data bus pins (D7D0), RD, WR, CS, and address inputs A1 and A0. Address inputs are present to select any of the four internal registers.
used for programming, reading, or writing to a counter

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 Timer zero generates an 18.2 Hz signal that interrupts the microprocessor at interrupt vector 8 for a clock tick.
often used to time programs and events in DOS

Timer 1 is programmed for 15 s, used on the PC to request a DMA action used to refresh the dynamic RAM. Timer 2 is programmed to generate a tone on the PC speaker.

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Pin Definitions for 8254 A0, A1

The address inputs select one of four internal registers within the 8254. See Table 114 for the function of the A1 and A0 address bits.

CLK
The clock input is the timing source for each of the internal counters. This input is often connected to the PCLK signal from the microprocessor system bus controller.
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CS
Chip select enables 8254 for programming and reading or writing a counter.

G
The gate input controls the operation of the counter in some modes of operation

GND
Ground connects to the system ground bus.
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OUT
A counter output is where the waveform generated by the timer is available.

RD
Read causes data to be read from the 8254 and often connects to the IORC signal.

Vcc
Power connects to the +5.0 V power supply.
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WR
Write causes data to be written to the 8254 and often connects to write strobe IOWC.

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Programming the 8254

Each counter is programmed by writing a control word, followed by the initial count.
fig 1134 lists the program control word structure

The control word allows the programmer to select the counter, mode of operation, and type of operation (read/write).
also selects either a binary or BCD count

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Figure 1134 The control word for the 8254-2 timer.

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 Each counter may be programmed with a count of 1 to FFFFH; A count of 0 is equal to FFFFH+l (65,536) or 10,000 in BCD. Timer 0 is used in the PC with a divide-by count of 64K (FFFFH) to generate the 18.2 Hz (18.196 Hz) interrupt clock tick.
timer 0 has a clock input frequency of 4.77 MHz + 4 or 1.1925 MHz

The order of programming is important for each counter, but programming of different counters may be interleaved for better control.
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Modes of Operation
six modes (05) of available to each of the 8254 counters each mode functions with the CLK input, the gate (G) control signal, and OUT signal
Figure 1135 The six modes of operation for the 8254-2 programmable interval timer. The G input stops the count when 0 in modes 2, 3, and 4.
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Mode 0
Allows 8254 to be used as an events counter. Output becomes logic 0 when the control word is written and remains until N plus the number of programmed counts. Note that gate (G) input must be logic 1 to allow the counter to count. If G becomes logic 0 in the middle of the count, the counter will stop until G again becomes logic 1.
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Mode 1
Causes function as a retriggerable, monostable multivibrator (one-shot). G input triggers the counter so it develops a pulse at the OUT connection that becomes logic 0 for the duration of the count.
if the count is 10, the OUT connection goes low for 10 clocking periods when triggered

If G input occurs within the output pulse, the counter is reloaded and the OUT connection continues for the total length of the count.
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Mode 2
Allows the counter to generate a series of continuous pulses one clock pulse wide.
pulse separation is determined by the count

For a count of 10, output is logic 1 for nine clock periods and low for one clock period. The cycle is repeated until the counter is programmed with a new count or until the G pin is placed at logic 0.
G input must be logic 1 for this mode to generate a continuous series of pulses
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Mode 3
Generates a continuous square wave at the OUT connection, provided the G pin is logic 1. If the count is even, output is high for one half of the count and low for one half of the count. If the count is odd, output is high for one clocking period longer than it is low.
if the counter is programmed for a count of 5, the output is high for three clocks and low for two clocks
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Mode 4
Allows a single pulse at the output. If count is programmed as 10, output is high for 10 clocking periods and low for one period.
the cycle does not begin until the counter is loaded with its complete count

Operates as a software triggered one-shot. As with modes 2 and 3, this mode also uses the G input to enable the counter.
G input must be logic 1 for the counter to operate for these three modes
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Mode 5
A hardware triggered one-shot that functions as mode 4.
except it is started by a trigger pulse on the G pin instead of by software

This mode is also similar to mode 1 because it is retriggerable.

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Generating a Waveform with the 8254

Fig 1136 shows an 8254 connected to I/O ports 0700H, 0702H, 0704H, and 0706H of an 80386SX. The addresses are decoded by using a PLD that also generates a write strobe signal for the 8254, which is connected to the low-order data bus connections.

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Figure 1136 The 8254 interfaced to an 8 MHz 8086 so that it generates a 100 KHz square wave at OUT0 and a 200 KHz continuous pulse at OUT1.

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 The PLD also generates a wait signal for the microprocessor that causes two wait states when the 8254 is accessed. The wait state generator connected to the microprocessor actually controls the number of wait states inserted into the timing. Example 1124 lists the program that generates a 100 KHz square-wave at OUT0 and a 200 KHz continuous pulse at OUT1.

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Reading a Counter
Each counter has an internal latch read with the read counter port operation.
the latches will normally follow the count

If counter contents are needed, the latch can remember the count by programming the counter latch control word. See Figure 1137.
counter contents are held in a latch until read

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Figure 1137 The 8254-2 counter latch control word.

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 When a read from the latch or counter is programmed, the latch tracks the contents. When necessary for contents of more than one counter to be read at the same time, the read-back control word is used Illustrated in Figure 1138.

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Figure 1138 The 8254-2 read-back control word.

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 With the read-back control word, the CNT bit is logic 0 to cause the counters selected by CNT0, CNT1, and CNT2 to be latched. If the status register is to be latched, then the bit is placed at logic 0. Figure 1139 shows the status register, which shows:
the state of the output pin whether the counter is at its null state (0) how the counter is programmed

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Figure 1139 The 8254-2 status register.

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DC Motor Speed and Direction Control

An application of 8254 is as a motor speed controller for a DC motor. Fig 1140 shows the schematic diagram of the motor and associated driver circuitry. It also illustrates the interconnection of the 8254, a flip-flop, and the motor and its driver.

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Figure 1140 Motor speed and direction control using the 8254 timer.

if Q output of the 74ALS112 is logic 1, the motor spins in its forward direction if logic 0, the motor spins in reverse if flip-flop output alternates between logic 1 and 0, the motor spins in either direction at various speeds if the duty cycle of the Q output is 50%, the motor will not spin at all and exhibits some holding torque

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 Fig 1141 shows some timing diagrams and effects on the speed/direction of the motor. Each counter generates pulses at different positions to vary the duty cycle at the Q output of the flip-flop. This output is also called pulse width modulation. Example 1125 lists a procedure that controls the speed and direction of the motor.

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Figure 1141 Timing for the motor speed and direction control circuit (a) No rotation, (b) high-speed rotation in the reverse, and (c) high-speed rotation, forward direction.

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116 ANALOG-TO-DIGITAL (ADC) & DIGITAL-TO-ANALOG (DAC) CONVERTERS

These devices are used to interface the microprocessor to the analog world. Many events monitored and controlled by the microprocessor are analog events. These range from monitoring all forms of events, even speech, to controlling motors and like devices.
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The DAC0830 Digital-to-Analog Converter

A fairly common and low-cost digital-to-analog converter is the DAC0830.
a product of National Semiconductor Corp

An 8-bit converter that transforms an 8-bit binary number into an analog voltage. Other converters are available that convert from 10-, 12-, or 16-bit binary numbers into analog voltages.
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 The number of voltage steps generated by the converter is equal to the number of binary input combinations.
an 8-bit converter generates 256 voltage levels a 10-bit converter generates 1024 levels

The DAC0830 is a medium-speed converter that transforms a digital input to an analog output in approximately 1.0 s.

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 Figure 1148 shows pin-outs of a DAC0830. The device has eight data bus connections for the application of the digital input code. Analog outputs labeled IOUT1 & IOUT2 are inputs to an external operational amplifier. Because this is an 8-bit converter, its output step voltage is defined as VREF (reference voltage), divided by 255.
the step voltage is often called the resolution of the converter

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Figure 1148 The pin-out of the DAC0830 digital-to-analog converter.

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Internal Structure of the DAC0830

Fig 1149 shows the internal structure. This device contains two internal registers.
the first is a holding register the second connects to the R2R internal ladder converter

The two latches allow one byte to be held while another is converted. The first latch is often disabled and the second for entering data into the converter.
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Figure 1149 The internal structure of the DAC0830.

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 Both latches within the DAC0830 are transparent latches.

when G input is logic 1, data pass through when G input becomes logic 0, data are latched

The output of the R2R ladder within the converter appears at IOUT1 and IOUT2. These outputs are designed to be applied to an operational amplifier such as a 741 or similar device.

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Connecting the DAC0830 to the Microprocessor.

A PLD is used to decode the DAC0830 at I/O port address 20H.
when an OUT 20H,AL instruction is executed, contents of data bus connections AD0AD7 are passed to the converter in the DAC0830

The 741 operational amplifier, along with the 12 V zener reference voltage, causes the fullscale output voltage to equal +12 V. See Fig 1150.
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Figure 1150 A DAC0830 interfaced to the 8086 microprocessor at 8-bit I/O location 20H.

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The ADC080X Analog-to-Digital Converter

A common, low-cost ADC, compatible with a wide range of microprocessors.
while there are faster ADCs available with more resolution, this device is ideal for applications that do not require a high degree of accuracy

ADC080X requires up to 100 s to convert an analog input voltage into a digital output code. Figure 1151 shows the pin-out of the ADC0804 converter.
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Figure 1151 The pin-out of the ADC0804 analog-to-digital converter.

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 To operate the converter, the WR pin is pulsed with CS grounded to start the conversion process. See Fig 1152 for a timing diagram that shows the interaction of the control signals. If a time delay is used that allows at least 100 s of time, there is no need to test INTR pin. Another option is to connect the INTR pin to an interrupt input, so when the conversion is complete, an interrupt occurs.
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Figure 1152 The timing diagram for the ADC0804 analog-to-digital converter.

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The Analog Input Signal

Before ADC0804 can be connected, the two analog inputs must be understood:
VIN(+) and VIN()

These differential inputs are summed by the operational amplifier to produce a signal for the internal analog-to-digital converter. These inputs are connected to an internal operational amplifier as shown in Fig 1153.

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Figure 1153 The analog inputs to the ADC0804 converter. (a) To sense a 0- to +5.0 V input. (b) To sense an input offset from ground.

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Generating the Clock Signal

ADC0804 requires a clock source to operate. It can be an external clock applied to CLK IN pin or can be generated with an RC circuit.
permissible range of clock frequencies is 100 KHz - 1460 KHz. desirable to use a frequency as close as possible to 1460 KHz so conversion time is minimized

If generated with an RC circuit, CLK IN and CLK R pins are connected to an RC circuit, as illustrated in Figure 1154.
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Figure 1154 Connecting the RC circuit to the CLK IN and CLK R pins on the ADC0804.

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Connecting the ADC0804 to the Microprocessor

ADC0804 interfaced to an 8086 is illustrated in Figure 1155.
VREF is not attached to anything, which is normal

Suppose ADC0804 is decoded at I/O port address 40H for the data and address 42H for INTR. The procedure to read data is listed in Example 1129.
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Figure 1155 The ADC0804 interfaced to the 8086 microprocessor.

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Using the ADC0804 and the DAC0830

This illustrates an example using an ADC0804 and a DAC0830 to capture and replay audio signals or speech.
a speech synthesizer has been used in the past to generate speech, but quality was poor

For human quality speech, we can use an ADC0804 to capture an audio signal and store it for later playback through a DAC0830.
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 Fig 1156 shows circuitry required to connect the ADC0804 at I/O ports 0700H and 0702H. The DAC0830 is interfaced at I/O port 704H.
These ports are in the low bank of a 16-bit microprocessor such as the 8086/80386SX

The software appears in Example 1130. It reads a 1-second burst of speech and plays it back 10 times.

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Figure 1156 A circuit that stores speech and plays it back through the speaker.

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 A procedure called READS reads the speech. A second, PLAYS, plays it back. The speech is sampled and stored in a section of memory called WORDS. The sample rate is chosen at 2048 samples per second, which renders acceptablesounding speech.

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