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Multiprocessors Interconnection Networks

The document discusses different methods for connecting processors in multiprocessor systems, including shared bus, multiple bus, and multistage interconnection networks. It describes bus arbitration schemes used in shared bus systems and different topologies for interconnecting processors and memory, such as crossbar, single-stage, and multistage networks. Classification criteria for multistage interconnection networks include blocking, rearrangeable, and non-blocking networks.

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Paul Corsina
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185 views

Multiprocessors Interconnection Networks

The document discusses different methods for connecting processors in multiprocessor systems, including shared bus, multiple bus, and multistage interconnection networks. It describes bus arbitration schemes used in shared bus systems and different topologies for interconnecting processors and memory, such as crossbar, single-stage, and multistage networks. Classification criteria for multistage interconnection networks include blocking, rearrangeable, and non-blocking networks.

Uploaded by

Paul Corsina
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Considered as the simplest way to connect multiprocessor systems A system consists of N processors, each having its own cache,

connected by a shared bus

A multiple bus multiprocessor system uses several parallel buses to interconnect multiple processors and multiple memory modules. Connection schemes: MBFBMC MBSBMC MBPBMC MBCBMC

Has all memory modules connected to all buses

Has each memory module connected to a specific bus

Has each memory module connected to a subset of buses

Has memory modules grouped into classes whereby each class is connected to a specific subset of buses

Bus arbitration is required in order to resolve the bus contention that takes place when more than one processor competes to access the bus. The process of passing bus mastership from one processor to another is called handshaking and requires the use of two control signals: Bus request Bus grant

A third signal, called bus busy, is usually used to indicate whether or not the bus is currently being used. In deciding which processor gains control of the bus, the bus arbitration logic uses a predefined priority scheme. Among the priority schemes used are:
Random priority Simple rotating priority Equal priority Least recently used priority (LRU)

The crossbar can provide simultaneous connections among all its inputs and all its outputs.

The crossbar contains a switching element (SE) at the intersection of any two lines extended horizontally or vertically inside the switch.
Straight and Diagonal Switch Setting

In this case, a single stage of switching elements (SEs) exists between the inputs and the outputs of the network. The simplest switching element that can be used is the 2 x 2 SE. The four possible settings that an SE can assume are: Straight Exchange Upper-broadcast Lower-broadcast

In this type of network, connections among processors and memory modules are made using simple switches.

Three basic interconnection topologies exist: Crossbar Single-stage Multistage

A number of classification criteria exist for MINs. Among these criteria is the criterion of blockage.

According to this criterion, MINs are classified as follows: Blocking Networks Rearrangeable Networks Non-blocking Networks

Blocking networks possess the property that in the presence of a currently established interconnection between two arbitrary unused input and output may or may not be possible.

Examples of blocking networks include: Omega Banyan Shuffle-exchange Baseline

Rearrangeable networks are characterized by the property that it is always possible to rearrange already established connections in order to make allowance for other connections to be established simultaneously.

The well-known example of this network is the Benes.

Non-blocking networks are characterized by the property that in the presence of a currently established connection between any pair of input/output, it will always be possible to establish a connection between any arbitrary unused pair of input/output. The Clos is a well-known example of non-blocking networks.

Static (fixed) interconnection networks are characterized by having fixed paths, unidirectional or bidirectional, between processors. Two types: Completely Connected Networks (CCNs) Limited Connection Networks (LCNs)

Each node is connected to all other nodes in the network


Guarantee fast delivery of messages from any source node to any destination node Routing of messages between nodes becomes a straightforward task

In LCNs, communications between some nodes have to be routed through other nodes in the network.

Two other conditions seem to have been imposed by the existence of limited interconnectivity in LCNs include: the need for a pattern of interconnection among nodes the need for a mechanism for routing messages around the network until they reach their destination

Regular Interconnection Patterns for LCNs: a) Linear array Network b) Ring Network c) Two-dimensional Array Network d) Tree Network e) Three-cube Network

In a cube-based multiprocessor system, processing elements are positioned at the vertices of the graph. Edges of the graph represent the point-to-point communication links between processors.

N represents the number of inputs (outputs) while m represents the number of buses.

The cost of the crossbar system can be measured in terms of the number of switching elements (cross points) required inside the crossbar. For an N x N crossbar, the rate of cost is given by O(N2).

The crossbar possesses a constant rate of delay given by O(1).


It is a non-blocking network. It can be affected by a single-point failure.

The cost of a multiple-bus system is measured in terms of the number of buses used, O(B). The multiple bus possesses an O(B x N) rate of delay growth.

It is a blocking network.
Multiple bus multiprocessor organization offers the desirable feature of being highly reliable and fault-tolerant.

The network cost, measured in terms of the total number of switching elements (SEs), is O(N x log2 N).
The time complexity, measured by the number of SEs along the path from input to output, is O(log2 N). It is a blocking network. MINs are vulnerable to single-point failure. They are characterized as being 0-fault tolerant.

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