CMOS Analog Design Using All-Region MOSFET

Modeling
1

CMOS Analog Design Using
All-Region MOSFET Modeling

Chapter 10
Fundamentals of sampled-data
circuits
CMOS Analog Design Using All-Region MOSFET
Modeling
2
MOS sample-and-hold circuits
Basic MOS sample-and-hold circuit (the circuit implements a track-
and-hold function, but we adopt the term sample-and-hold, the most
commonly used in the literature)
CMOS Analog Design Using All-Region MOSFET
Modeling
3
Thermal noise in S/H
Equivalent circuit of the S/H
with the switch on and v
i
= 0.
Power spectral density of the noise voltage across the capacitor
CMOS Analog Design Using All-Region MOSFET
Modeling
4
( ) ( )
s
s t t nT o

( ) ( )
s
x x t s t =
( ) ( )
1
2 2 2
s s
m
s
X j f X j f jm f
T
t t t
+
=
=

Idealized sampling
CMOS Analog Design Using All-Region MOSFET
Modeling
5
2
CN
v
f A
f
s

2f
NB

f
2 4 1
(2 ).
4
NB ON
ON
s s ON s
f kTR kT
kTR
f f R C Cf
= =
Aliasing of thermal noise
The resistor noise power spectral
density is multiplied by 2 f
NB
/f
s
:
Simplified representation of the aliasing of thermal
noise due to sampling for the case 2f
NB
/f
s
= 6.
s
s
kT kT
f
Cf C
=
The fully aliased thermal noise in the
(useful) Nyquist bandwidth -f
s
/2 < f < f
s
/2 is
CMOS Analog Design Using All-Region MOSFET
Modeling
6
/2
2
2 2
/2
1
12
rms
e e de
A
A
A
| |
= =
|
A
\ .
}
2
12
kT
C
A
s
2
2
12
B
FS
C kT
V
| |
>
|
\ .
Number of bits
(B)
Capacitance
(C)
8 3.3 fF
12 0.83 pF
14 13.3 pF
16 213 pF
20 55 nF
Thermal vs. quantization noise
Quantization error of digitized analog
waveform. V
FS
is the full-scale voltage
range and is the size of the LSB
V
FS
= 1 V and T=300 K
CMOS Analog Design Using All-Region MOSFET
Modeling
7
0, DD T P
DD
P
V V
V
n
+

0, DD T N
N t
V V
n |

, , on N on P
g g +
V
in

DD
V 0
, on N
g
, on P
g
Illustration of the distortion
produced by the input-
dependent delay of the MOS
S/H in the tracking mode
Switch on-resistance
Variation of the on-conductance of the
nMOS, pMOS, and CMOS switches with
the input voltage.
CMOS Analog Design Using All-Region MOSFET
Modeling
8
Linearization of the MOS sampling switch
Linearized S/H with output buffer
Sampling instant
variation (a) ordinary
S/H; (b) linearized S/H
CMOS Analog Design Using All-Region MOSFET
Modeling
9
5
2
s
ON H
T
R C >
1
10
s
ON H
f
R C
<
1
ON
I
R
W
Q
L

=
'
2
ON
I
L
R
Q
=
2 2
1
10 10 5
I
s
ON H H
Q
V
f
R C L C L

A
< = =
Charge injection by the switch - 1
For V = 1mV, calculate the maximum clock frequencies for effective
channel length of 1 m, 0.316 m and 100 nm = 500 cm2/Vs
Answer: f
s
: 10 MHz, 100 MHz, and 1 GHz, for 1 m, 0.316 m, and 100 nm
channel lengths, respectively.
2
I
H
Q
V
C
A = For
CMOS Analog Design Using All-Region MOSFET
Modeling
10
Charge injection by the switch - 2
Charge injection cancellation techniques: (a) short fall time of
the clock and half-sized dummy switches, (b) fully-differential
structure
CMOS Analog Design Using All-Region MOSFET
Modeling
11
Low-voltage S/H circuits - 1
On-conductance of a CMOS switch for two different supply
voltages: (a) V
DD
= 5V and (b) V
DD
= 1.5 V
CMOS Analog Design Using All-Region MOSFET
Modeling
12
Low-voltage S/H circuits - 2
(a) Available output swing obtained by dc-
shifting the input signal applied to the n- and
p-MOS switches (V
DSsat
is the voltage
margin to either V
DD
or ground required for
the proper operation of the blocks, e.g.,
amplifiers, connected to the switches); (b)
Low-voltage S/H that provides dc bias for
proper operation of both switches
CMOS Analog Design Using All-Region MOSFET
Modeling
13
Low-voltage S/H circuits - 3
Bootstrapped MOS switch: (a) Simplified schematic and
(b) Input (source) and clock (gate) signals
CMOS Analog Design Using All-Region MOSFET
Modeling
14
T is a random variable the standard deviation of which is
called (aperture) jitter t
a
, measured in (rms) seconds.

Typical clocks: jitter of 100 ps rms, high quality clocks jitter of
1 ps rms.

the signal-to-noise (SNR) of the S/H due to clock jitter is given
by
CMOS Analog Design Using All Region MOSFET
Modeling
14
( )
2
10 10 2
1
2 2
10log 20log 2
2
FS
s a
a
s FS
V
SNR f
f V
t t
t
t
| |
| |
|
|
\ .
|
= =
|
| |
|
|
\ .
\ .
Jitter analysis
CMOS Analog Design Using All-Region MOSFET
Modeling
15
Resolution vs. sampling rate in A/D
Resolution, in number of bits, as stated by the manufacturer,
versus sampling rate, for A/D converters implemented in silicon
CMOS Analog Design Using All-Region MOSFET
Modeling
16
1 1

A
q C v =
2 1

B
q C v =
( )
1 2 1

A B
q q q C v v A = =
( )( )
1
/ /
av A B
i q T C T v v = A A =
1 1 1
/ 1/
s
R T C C f = =


Basics of switched-capacitor (SC) filters
Thus, on average, the switched capacitor behaves as a resistor with
its resistance value given by
CMOS Analog Design Using All-Region MOSFET
Modeling
17
( ) ( )
( ) ( )
- / 2 - / 2

+ =
= +
R R n O n
R O n
C v t T Cv t T
C C v t
( ) ( ) / 2
o n o n
v t T v t T =
( ) ( ) / 2
R n R n
v t T v t T =
( ) ( ) ( ) ( )
R R n o n R o n
C v t T Cv t T C C v t + = +
( )
2 2 2
1 1
R R o R o
C V z CV z C C V
| | |
+ = +
2
2
1
1
1 /( )
o R
R R R
V C z
V C C z C C C
|
|

=
+ +
First-order low-pass SC filter
CMOS Analog Design Using All-Region MOSFET
Modeling
18
( )
( )
( )
/ 2
1 1
2 2
/ 2
1
1 sin / 2
j T
j T
j T
T
C C e
H z e
C e C j T T
e
e
e
e
e e

= = =

( )
1
1
2
1
j T
T
C
H z e
C j T
e
e
e
<<
= ~
Switched-capacitor integrators 1
(a) Continuous-time and (b) parasitic-sensitive switched-capacitor
integrators.
CMOS Analog Design Using All-Region MOSFET
Modeling
19
v
2

v
1

C
1

C
2

|
1

|
2
|
1

|
2

(a)
v
2

v
1

C
1

C
2

|
1

|
2

|
1

|
2

(b)
( )
( )
( )
1
2
1/ 2
2
1
12
1
1 2
1
V z
C z
H z
V z C z
|
|

= = +

( )
( )
( )
2
2
1
2
1
22
1
1 2
1
V z
C z
H z
V z C z
|
|

= = +

( )
( )
( )
1
1
2
1
11
1
1 2
1
1
V z
C
H z
V z C z
|
|
= =

( )
( )
( )
2
1
1/ 2
2
1
21
1
1 2
1
V z
C z
H z
V z C z
|
|

= =

Switched-capacitor integrators 2
(a) Non-inverting and (b) inverting parasitic-insensitive integrators
CMOS Analog Design Using All-Region MOSFET
Modeling
20
( )
0 A A A
q C v C f v v = =
( )
0 B B B
q C v C f v v = =
0
0
( )
( )
B B B
A A A
C q area C
q C area C
= =
SC circuits as charge processors - 1
(a) Elementary charge mirror and (b) Basic SC signal processing blocks
CMOS Analog Design Using All-Region MOSFET
Modeling
21
( ) ( ) ( )
( ) ( )
0 0
0 0
/ 2

+ +
= +
E F
I A B
A B
A A
C C
q nT T q nT q nT
C C
q nT q nT T
( ) ( ) ( )
0
0
G
A B B
A
C
q nT T q nT q nT T
C
= +
( ) ( ) ( ) ( )
( ) ( )
0 0 0 0
0 0 0 0

H J D D
B C A A
B C A A
C C
C C C C
q nT q nT q nT q nT T
C C C C
q nT q nT T
+ +
= +




SC circuits as charge processors - 2
Third-order SC filter
CMOS Analog Design Using All-Region MOSFET
Modeling
22
SC circuits as charge processors - 3
Signal-flow graph of the third-order SC filter
CMOS Analog Design Using All-Region MOSFET
Modeling
23
SC circuits as charge processors - 4
Measured output waveforms at (a) an intermediate node and (b)
output node of an SC filter implemented with nonlinear capacitors,
with the exception of the linear input and output capacitors