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System Software Unit 1

The document describes the architecture of the Simplified Instructional Computer (SIC) and its extension SIC/XE. It discusses the following key points in 3 sentences: The SIC has 215 bytes of memory organized into words of 3 bytes each. It has registers including an accumulator, index, and linkage registers. The SIC uses 24-bit two's complement integers and has instruction formats to specify opcodes and addressing modes including direct and indexed addressing.

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100 views

System Software Unit 1

The document describes the architecture of the Simplified Instructional Computer (SIC) and its extension SIC/XE. It discusses the following key points in 3 sentences: The SIC has 215 bytes of memory organized into words of 3 bytes each. It has registers including an accumulator, index, and linkage registers. The SIC uses 24-bit two's complement integers and has instruction formats to specify opcodes and addressing modes including direct and indexed addressing.

Uploaded by

Hsejar Candy
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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The Simplified Instructional Computer (SIC)

SIC is a hypothetical computer that includes the hardware features most often found on real machines Two versions of SIC
standard

model extension version

Chap 1

SIC Machine Architecture (1/5)

Memory
215

bytes in the computer memory 3 consecutive bytes form a word 8-bit bytes

Registers
Mnemonic Number Special use A 0 Accumulator; used for arithmetic operations X 1 Index register; used for addressing L 2 Linkage register; JSUB PC 8 Program counter SW 9 Status word, including CC

Chap 1

SIC Machine Architecture (2/5)

Data Formats
are stored as 24-bit binary numbers; 2s complement representation is used for negative values No floating-point hardware
Integers

Instruction Formats
opcode (8)

address (15)

Addressing Modes
Mode Direct Indexed Indication x=0 x=1 Target address calculation TA=address TA=address+(X)
Chap 1

SIC Machine Architecture (3/5)

Instruction Set
load

and store: LDA, LDX, STA, STX, etc. integer arithmetic operations: ADD, SUB, MUL, DIV, etc.
All

arithmetic operations involve register A and a word in memory, with the result being left in the register

comparison:
COMP

COMP

compares the value in register A with a word in memory, this instruction sets a condition code CC to indicate the result
Chap 1

SIC Machine Architecture (4/5)

Instruction Set
conditional
these

jump instructions: JLT, JEQ, JGT

instructions test the setting of CC and jump accordingly

subroutine

linkage: JSUB, RSUB

JSUB jumps to the subroutine, placing the return address in register L RSUB returns by jumping to the address contained in register L

Chap 1

SIC Machine Architecture (5/5)

Input and Output


Input

and output are performed by transferring 1 byte at a time to or from the rightmost 8 bits of register A The Test Device (TD) instruction tests whether the addressed device is ready to send or receive a byte of data Read Data (RD) Write Data (WD)

Chap 1

SIC Programming Examples

Data movement Fig. 1.2 Arithmetic operation Fig. 1.3 Looping and indexing Fig. 1.4, Fig. 1.5 Input and output Fig. 1.6 Subroutine call Fig. 1.7

Chap 1

SIC Programming Examples (Fig 1.2)


-- Data movement
ALPHA FIVE CHARZ C1 RESW WORD BYTE RESB . . LDA STA LDCH STCH (a) 1 5 CZ 1

No memory-memory move instruction 3-byte word:

LDA, STA, LDL, STL, LDX, STX LDCH, STCH

FIVE ALPHA CHARZ C1

1-byte:

Storage definition
WORD, RESW BYTE, RESB

SIC Programming Examples (Cont.)

All arithmetic operations are performed using register A, with the result being left in register A.
BETA=ALPHA+INCR-ONE DELTA=GAMMA+INCR-ONE

Chap 1

SIC Programming Example -- Arithmetic operation (Fig 1.3)

BETA=ALPHA+INCR-ONE DELTA=GAMMA+INCR-ONE

SIC Programming Example


-- Looping and indexing (Fig. 1.4)

Chap 1

SIC Programming Example


-- Looping and indexing (Fig. 1.5)

Arithmetic

Arithmetic operations are performed using register A, with the result being left in register A

Looping (TIX)
(X)=(X)+1 compare

with operand

set

CC

GAMMA[I]=ALPHA[I]+BETA[I] I=0 to 100


Chap 1

SIC/XE Machine Architecture (1/4)

Memory
220

bytes in the computer memory

More Registers
Mnemonic Number Special use B 3 Base register; used for addressing S 4 General working register T 5 General working register F 6 Floating-point acumulator (48bits)

Chap 1

SIC/XE Machine Architecture (2/4)

Data Formats
Floating-point
frac:

data type: frac*2(exp-1024)

0~1 exp: 0~2047


s exponent (11)

fraction (36)

Instruction Formats
Format 1 op(8) Format 2 op(8) r1(4) r2(4)

Format 3 op(6)
Format 4 op(6)

e=0 n I xbp e
e=1 n I xbpe

disp(12)
address (20)

Chap 1

SIC/XE Machine Architecture (3/4)

How to compute TA?


Mode Base relative PC-relative Direct Indexed Indication b=1, p=0 b=0, p=1 b=0, p=0 x=1 Target address calculation TA=(B)+disp (0<=disp<=4095) TA=(PC)+disp (-2048<=disp<=2047) TA=disp (format 3) or address (format 4) TA=TA+(X) operand (TA) (TA) (TA) (TA)

How the target address is used?


Mode Indication immediate addressingi=1, n=0 indirect addressing i=0, n=1 operand value TA ((TA)) SIC instruction (all end with 00) SIC/XE instruction

simple addressing

i=0, n=0 i=1, n=1

Note: Indexing cannot be used with immediate or indirect addressing modes

Chap 1

Example of SIC/XE instructions and addressing modes

Chap 1

SIC/XE Machine Architecture (4/4)

Instruction Set
new

registers: LDB, STB, etc. floating-point arithmetic: ADDF, SUBF, MULF, DIVF register-register arithmetic: ADDR, SUBR, MULR, DIVR supervisor call: SVC
generates

an interrupt for OS (Chap 6)

Input/Output
SIO,

TIO, HIO: start, test, halt the operation of I/O device (Chap 6)

Chap 1

SIC/XE Programming Examples (Fig 1.2)


ALPHA FIVE CHARZ C1 RESW WORD BYTE RESB . . LDA STA LDCH STCH (a) 1 5 CZ 1 ALPHA C1 RESW RESB . . . LDA STA LDA STCH 1 1

FIVE ALPHA CHARZ C1

#5 ALPHA #90 C1

(b)

SIC/XE Programming Example


-- Looping and Indexing Example (Fig 1.4)

SIC/XE Programming Example


-- Looping and indexing (Fig 1.5)

SIC/XE Programming Example

data movement
#:

immediate addressing for SIC/XE S,X

arithmetic
ADDR

Looping (TIXR T)
(X)=(X)+1
compare set

with register specified

CC

COMPR X,T
Chap 1

SIC Programming Example


-- Sample Input and Output (Fig 1.6)

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