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FINFET (Multiple Gate Transistors)

This document discusses FinFET technology as the future of VLSI design. It begins by covering Moore's Law and the need to scale down CMOS dimensions. Short channel effects that arise during scaling like DIBL, subthreshold conduction, and hot carriers are discussed. FinFET technology is introduced as a way to better control the channel and reduce these effects. FinFET fabrication processes, types (bulk vs SOI), advantages, and applications are summarized. The document concludes that FinFET allows further scaling in support of Moore's Law and provides benefits like greater speed and reduced short channel effects.

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Nitin Mathur
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248 views

FINFET (Multiple Gate Transistors)

This document discusses FinFET technology as the future of VLSI design. It begins by covering Moore's Law and the need to scale down CMOS dimensions. Short channel effects that arise during scaling like DIBL, subthreshold conduction, and hot carriers are discussed. FinFET technology is introduced as a way to better control the channel and reduce these effects. FinFET fabrication processes, types (bulk vs SOI), advantages, and applications are summarized. The document concludes that FinFET allows further scaling in support of Moore's Law and provides benefits like greater speed and reduced short channel effects.

Uploaded by

Nitin Mathur
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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By

Martha Sivaram EC124561 Saurabh Dixit EC124570 VLSI System Design

INTRODUCTION
Moores law
The number of transistors on a given silicon chip of unit inch doubles in every 18 months.

CONTD. Scaling down CMOS:


Reducing the dimensions of the transistor such as length, thereby increase the number of transistors that fit in a single chip.

Short Channel :
Length of the channel is comparable with that of the depletion layer width.

L W

CONTD. Short channel effects :


As the length Of the channel is reduced day by day short channels effects have come into existence such as DIBL, Hot electron effect etc

FINFET Technology :
FINFET is a multi gate transistor that provides better control of the channel .

SHORT CHANNEL EFFECTS


DIBL :
1) DIBL stands for drain induced barrier lowering. 2) MOSFET threshold voltage is reduced due to reduction in channel length 3) Drain Voltage is also responsible for controlling drain current. 4) As channel length reduces this effect is increasing.

CONTD.

CONTD
Sub threshold conduction
1) Drain current flows in weak inversion region. Gate Voltage< Threshold Voltage
2) As the channel length is reduced this has become significant due to power dissipation in MOS off state 3) Drain Voltage is also responsible for controlling drain current. 4) DIBL is one of the reasons for this effect

CONTD
Figure below shows the sub threshold conduction in a MOS

CONTD
Hot carriers :
1) This effect arises due to scaling down of the physical dimensions but not supply voltages equivalently. 2) Large electric field at the gate and sio2 interface. 3) Gate leakage current is generated 4) Predominant in short channel devices

CONTD.
Punch Through :
1) Source and drain depletion regions contact. 2) With reduction in the channel length if the drain voltage is increased punch through occurs early. 3) Large amount of current passes from source to drain 4) If we leave the device in the same state without any action the device will breakdown due to excess current and fail to operate at its normal functionality

PARASITICS
Figure below shows some of the parasitics available in a mosfet 1) Parasitic capacitances 2) Parasitic resistances

FINFET

Bulk nmos

Silicon on insulator

FinFet

CONTD.
Gate

Source

Drain

3D view of FinFET

3D view of multi-fin FinFET

CONTD.

Transistor structure is redefined. Transistor grows vertical so are considered as 3D Transistor

Channel is a thin silicon membrane or fin thus the name FINFET.


Better gate control over the channel. Provides greater level of scalability

TYPES OF FINFET
Based on the fabrication, FINFET are of two types 1) Bulk FINFET 2) SOI FINFET SOI FINFET are given priority over Bulk FINFET even though the cost of generation of bulk FINFET is less, due to 1) Reduction in few parasitic elements 2) Possibility of leakage current to substrate is less. 3) Doping is more complex in bulk FINFET, to reduce the leakage current.

CONTD.

Bulk FINFET

SOI FINFET

FINFET FABRICATION PROCESS


FinFETs are usually fabricated on an SOI substrate. It starts by patterning and etching thin fins on the SOI wafer using a hard mask. The hard mask is retained throughout the process to protect the fin.

The fin thickness is typically half or one third the gate length, so it is a very small dimension.
It is made by either e-beam lithography or by optical lithography using extensive line width trimming [7].

CONTD.

CHALLENGES FOR FINFET


The key challenges in FinFET fabrication are 1) The thin, uniform fin. 2) Reducing the source-drain series resistance. 3) A balance between the above two is needed as the fin is made more thin the series resistance increases there by increasing the power dissipation

ADVANTAGES OF FINFET
Some of the advantages of the FINFET are 1) Having better control of the channel under the gate. 2) Reduction in the sub threshold conduction 3) Less DIBL compared to planar CMOS 4) Reduction in parasitic element values 5) Ability to further scale down with control of short channel effects 6) Elimination of Vt variation due to Random dopant fluctuation

APPLICATION
1.

2.

Low power design in digital circuit, such as RAM, because of its low off-state current. Power amplifier or other application in analog area which requires good linearity.

CONCLUSION
FINFET provides the ability to scale down further which supports Moores law for few more years

Greater speed.
Reduced Short channel effects increases the reliability This is considered as the future of VLSI

REFERENCES
[1] Jurczak, M. Review of FINFET technology, SOI Conference, 2009 IEEE International [2] Daniel Rairigh, Limits of CMOS Technology Scaling and Technologies Beyond-CMOS, Student member IEEE [3] Yang-Kyu Choi, Sub-20 nm CMOS FinFET technologies, Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International [4] Chenming Hu, Thin-body FinFET as scalable low voltage transistor , VLSI Technology, Systems, and Applications (VLSI-TSA), 2012 International Symposium on [5] Goel, A, Parasitic Resistances, Capacitances, and Inductances ,Components, Circuits, Devices & Systems

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