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INTRODUCTION PROBLEM DEFINITION & JUSTIFICATION DELIVERABLES BNM_LVT_45NM LIBRARY

DESIGN FLOW DESIGN GUIDELINES BNM_LVT_45NM DESIGN DESIGN CHARACTERIZATION

SCHEMATIC VIEW LAYOUT VIEW ABSTRACT VIEW CHARACTERIZATION DATA LEF DEF

RESULTS AND DISCUSSION

CONCLUSION FUTURE SCOPE PAPER PUBLICATIONS

REFERENCES

Standard cell based design is the most practiced approach to implement an IC This design flow requires a set of logic cells whose characteristic behavior is well known Such a set of logic cells is collectively called as a Standard Cell Library. Constituents of CMOS Standard Cell Library

The components of a standard cell library are

Logical cells Buffer Cells Special Cells

University /

S.I No.,
1 2

Library name
VTVT OSU

Organisation Virginia tech Oklahoma state university North Carolina

Technology
250nm & 180nm 250nm &180 nm

NCSU State University Mississippi State

250 nm

4 4

MSU gpdk045

university Cadence

180nm 45nm

The BNM_LVT_45nm library contains the following deliverables

.lib (Liberty library file) .LEF(Library exchange format) .spi (Spice netlist) Schematic representation Layout View Abstract view Av_extracted view

Cell Name INVERTER BUFFER AND OR NAND

No., of Inputs 1 1 2,3,4 2,3,4 2,3,4

Drive strength 1X,2X,4X,16X,32X 1X,2X,4X,16X,32X 1X,2X,4X 1X,2X,4X 1X,2X,4X

NOR
AOI OAI XOR FULL ADDER MUX DFLIPFLOP CLK GATE CLK BUFFER FILLER CELLS

2,3,4
(21),(22),(211),(221),(222) (21),(22),(211),(221),(222) 2 3 2X1,4X1

1X,2X,4X
1X,2X,4X 1X,2X,4X 1X,2X

1X,2X 1X,2X 1X 1X

BNM_LVT_45NM library design

Schematic Entry

Pre Layout Simulation Library Verification

Layout

Extraction

Abstract(LEF/DE F)
Characterizati on
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Post Layout Simulation

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EDA Tool Name

Tool functionality

Cadence Virtuoso Schematic Editor XL

Cadence Virtuoso Analog Design Environment Cadence Spectre Simulator

Schematic Entry
Simulation Environment setup Spice Simulations /Functional Verification

Cadence Virtuoso Layout XL

Cadence Assura DRC, LVS / Cadence Physical Verification Cadence QRC

Layout Entry
Design Rule Check and Layout vs. Schematic verification Parasitic Extraction

Cadence Hierarchy Editor

Cadence Abstract Generator Cadence LEF/DEF

Back annotation
Abstract View generation LEF and DEF view generation

Cadence Encounter Library Characterizer

Characterization of Cells

Design Guidelines

 Cell height 3.36m 15 routing tracks

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Horizontal

Vertical

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Horizontal

15 Routing Tracks

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Vdd Rail

PMOS REGION Standard cell height Cell Origin NMOS REGION

Vss Rail

Design

Input file format

spice model files (.scs, .spi, .sp )

Output file format

Spice netlist (.scs, .spi, .sp )

Tool
Cadence Virtuoso Schematic

editor

 Tool Spectre Simulator in Cadence Virtuoso ADE

Input file format

Spice netlist (.scs, .spi, .sp )

Output file format

Intermediate layout data base in .oa (Open Access)

Tool
Cadence Virtuoso Layout editor

Input file format

Intermediate layout data base in .oa (Open Access)

Output file format

Circuit Spice netlist (.scs, .spi, .sp )

Tool
Cadence QRC extraction tool

Physical Simulation

Abstract View Generation

Cadence Abstract generator

Pin Information

LEF file generation

The LEF file for all cells is generated using the

Cadence Virtuoso Toolset. The LEF contains information about the physical characteristics of the cells

.Lib generation
Characterization of the BNM_LVT_45nm library cells

is carried out using Cadence Encounter Library Characterizer The Cadence Encounter Library Characterizer requires the extracted spice netlists of BNM_LVT_45nm Cells. The cells are characterized for different Process, voltage and temperature conditions through spice simulations. The characterization data is presented in a Liberty file format (.Lib)

The ELC tool must be configured as per the

requirements of the characterization process

The elccfg file is used to configure ELC.

It contains information about model files,

spice subcircuit definitions, process for which

the cells must be characterized etc.

ELC setup file

The ELC tool requires a setup file which contains

information about different process, voltage and temperature conditions to be considered for simulation.

Process Corners

Parameters
Min
Vdd

Typical 1V

MAX 1.1 V

0.9 V

Ambient
Temperature

0C

25C

40C

Different views of a cell in BNM_LVT_45nm library

Schematic Layout Abstract Spice netlist Extracted view LEF file Liberty library file DEF file

MACRO NOR2_X1 CLASS BLOCK ; ORIGIN 0 0 ; FOREIGN NOR2_X1 0 0 ; SIZE 1.275 BY 3.36 ; SYMMETRY X Y R90 ; PIN y DIRECTION OUTPUT ; USE SIGNAL ; PORT LAYER Metal1 ; RECT 1.025 1.02 1.16 1.08 ; END END y PIN B DIRECTION INPUT ; USE SIGNAL ; PORT LAYER Metal1 ; RECT 0.995 2.075 1.195 2.165 ; END END B

PIN A DIRECTION INPUT ; USE SIGNAL ; PORT LAYER Metal1 ; RECT 0.1 0.935 0.3 1.195 ; END END A PIN gnd! DIRECTION INOUT ; USE GROUND ; PORT LAYER Metal1 ; RECT 0.62 -0.06 0.68 0.025 ; END END gnd! PIN vdd! DIRECTION INOUT ; USE POWER ; PORT LAYER Metal1 ; RECT 0.18 3.3 0.24 3.42 ; END END vdd! OBS

LAYER Metal1 ; RECT 0 0 1.275 3.36 ; LAYER Metal2 ; RECT 0 0 1.275 3.36 ; LAYER Metal3 ; RECT 0 0 1.275 3.36 ; LAYER Metal4 ; RECT 0 0 1.275 3.36 ; LAYER Metal5 ; RECT 0 0 1.275 3.36 ; LAYER Metal6 ; RECT 0 0 1.275 3.36 ; LAYER Metal7 ; RECT 0 0 1.275 3.36 ; LAYER Metal8 ; RECT 0 0 1.275 3.36 ; LAYER Metal9 ; RECT 0 0 1.275 3.36 ; LAYER Metal10 ; RECT 0 0 1.275 3.36 ; LAYER Metal11 ; RECT 0 0 1.275 3.36 ; END END NOR2_X1

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VERSION 5.6 ; DIVIDERCHAR "/" ; BUSBITCHARS "[]" ;

DESIGN AND2_X1 ; UNITS DISTANCE MICRONS 2000 ;

COMPONENTS 11 ; - I__0 pmos1v_lvt_45 + PLACED ( 1370 3200 ) FN ; - I__1 nmos1v_lvt_46 + PLACED ( 1250 1080 ) FN ; - I__2 pmos1v_lvt_43 + PLACED ( 2550 2840 ) N ; - I__3 nmos1v_lvt_47 + PLACED ( 810 1080 ) FN ; - I__4 nmos1v_lvt_48 + PLACED ( 2250 670 ) N ; - I__5 pmos1v_lvt_49 + PLACED ( 770 3200 ) N ; - I__6 M1_PO_3 + PLACED ( 290 2220 ) N ; - I__7 M1_PO_3 + PLACED ( 1610 2650 ) N ; - I__8 M1_PO_3 + PLACED ( 2310 2080 ) N ; - I__9 M1_NWELL_1 + PLACED ( 180 3230 ) N ; - I__10 M1_PSUB_8 + PLACED ( 760 30 ) N ; END COMPONENTS
END DESIGN

Liberty file for AOI211_X1

AOI211_X1:
Features:
Strength Cell Area Function Type Input Output Power Supply 1X 4.7376m2 Y=!(((C1 & C2) | B) | A) Combinational A ,B ,C1,C2 Y Vdd -1V, Gnd -0V

AOI211_X1
Propagation delay[ns] 0.0231 1.2

Input Transition[ns]

Load Capacitance[fF]
A to Y Fall Rise Fall Rise Fall Rise Fall Rise

0.82
0.024328 0.055338 0.022713 0.051787 0.028018 0.036532 0.030519 0.042319

189.75
0.585933 1.87069 0.556589 1.86726 1.12892 1.97481 1.13184 1.9964

0.82
0.206251 0.25112 0.167128 0.258417 0.159901 0.213229 0.165951 0.249131

189.75
1.14821 2.2676 1.11221 2.33449 1.62 2.43432 1.60209 2.46087

B to Y
C1 to Y C2 to Y

Transition Delay of AOI211_X1

Output Transition[ns]

Input Transition[ns]

0.0231
0.82
0.015902 0.037977 0.013744 0.038034 0.020596 0.036356

1.2
189.75 0.82
0.171114 0.148659 0.170691 0.175089 0.181001 0.191706

Load Capacitance[fF] A to Y
Fall Rise B to Y Fall Rise C1 to Y C2 to Y Fall Rise

189.75
0.846717 2.43649 0.815712 2.43724 1.52304 2.61927

0.803832 2.438 0.764636 2.43745 1.51654 2.62274

Fall
Rise

0.020671
0.041368

1.52994
2.64366

0.162744
0.191893

1.52109
2.64294

Capacitance
Capacitance[fF] A B 1.09103 1.15921 0.931196 0.11872

Power
Leakage Power[nW]

0.251096

C1 C2

AOI211_X1
Dynamic power consumption
Dynamic Power Consumption[nW]

Input Transition[ns] Load Capacitance[fF]

0.0231 0.82 0.000471 0.002707 0.000273 0.002396 0.000188 0.001828 0.000174 189.75 0.076025 0.079261 0.076201 0.078959 0.076607 0.078421 0.076602 0.82 0.00102 0.002881 0.000873 0.002683 0.00041 0.002422 0.000207

1.2 189.75 0.07593 0.079247 0.076116 0.078947 0.07654 0.078469 0.076601

A to Y
B to Y C 1to Y C2 to Y

Fall Rise Fall Rise Fall Rise Fall

Target Library - 45nm technology Standard cell height 3.36m (149) Derivative library to gpdk045 It is a 15 track library Supports core power supply 1V Contains functional special cells filler cells Liberty file format for all cells synthesis LEF, DEF available for all cells Cadence Design tools used for entire design flow Low Vt transistors are used for all cells Cells are operable upto 125 Celsius Only Metal1,Metal2 and poly are used for intra-cell routing

The Standard cell library is technology dependent , hence as the technology shifts to newer sub nano geometry nodes, a new cell library must be developed. Optimized versions of BNM_LVT_45nm library can be developed focusing on either low power or high performance cells. It is also possible to scale down the library to sub-45nm technology.

Title of the Paper Accurate Power Measurement Methodology for VLSI Circuits Using CAD Tools Name of the conference

International Conference on Devices ,Circuits and Systems

IEEE xplore paper ID INSPEC Accession no: 12692787

ISBN no: 978-1-4577-1545-7

Venue Karunya Univeristy, Coimbatore, India

Dimitris Bekiaris, Antonis Papanikolaou, Giorgos Stamelos, Dimitrios Soudris, George Economakos and Kiamal Pekmestzi, A standard-cell library suite for deep-deep submicron CMOS technologies, 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), IEEE -2011 . Jianping Hu and Jun Wang Low Leakage Power Designs of Basic Standard Cells Using Gate-Length Biasing, IEEE 2011 Gerson Scartezzini, Ricardo Reis, Power Consumption in Transistor Networks versus in Standard Cells, IEEE 2011. Jeannette Donan Djigbenou, Thien Van Nguyen, Cheng Wei Ren, and Dong Sam Ha, Development of TSMC 0.25m Standard Cell Library ,IEEE 2007

Development and Distribution of TSMC 0.25 m Standard CMOS Library Cells,Jeannette Donan Djigbenou and Dong Sam Ha,VTVT (Virginia Tech VLSI for Telecommunications) Lab,IEEE 2007
Puneet Gupta, Andrew B. Kahng, Puneet Sharma, and Dennis Sylvester GateLength Biasing for Runtime-Leakage Control, IEEE 2006 Nguyen Minh Duc and Takayasu Sakurai Compact yet High-Performance (CyHP) Library for Short Time-to-Market with New Technologies,ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference, 2000 Asral bin Bahari Jambek, Ahmad Raif bin Mohd Noor Begand Mohd Rais Ahmad Standard Cell Library Development, IEEE 1999 J.L. Noullet, A. Ferreira-Noullet Do We Need So Many Cells For Digital ASIC Synthesis?, Institut National des Sciences Appliquees,Electron Technol (Warsaw). Vol. 32, No. 3, Pp. 272-276. 1999 .

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