15-213 Memory Technology March 14, 2000

Topics
Memory Hierarchy Basics Static RAM Dynamic RAM Magnetic Disks Access Time Gap

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Computer System
Processor
Reg

Cache Memory-I/O bus I/O controller

Memory

I/O controller
Display

I/O controller
Network

Disk
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Disk
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Levels in Memory Hierarchy

cache virtual memory

CPU regs Register size: speed: $/Mbyte: block size: 200 B 2 ns 8B

8B

C a c h e

32 B

Memory

8 KB

disk

Cache 32KB - 4MB 4 ns $100/MB 32 B

Memory 128 MB 60 ns $1.50/MB 8 KB

Disk Memory 20 GB 8 ms $0.05/MB

larger, slower, cheaper

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Scaling to 0.1m
Semiconductor Industry Association, 1992 Technology Workshop Projected future technology based on past trends 1992 Feature size: 0.5 1995 0.35 1998 0.25 2001 0.18 2004 0.12 2007 0.10

Industry is slightly ahead of projection

DRAM capacity: 16M

Prediction on track Chip area (cm2): 2.5

64M

256M

1G

4G

16G

Doubles every 1.5 years 4.0 6.0 8.0 10.0 12.5

Way off! Chips staying small

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Static RAM (SRAM)

Fast
~4 nsec access time

Persistent
as long as power is supplied no refresh required

Expensive
~$100/MByte 6 transistors/bit

Stable
High immunity to noise and environmental disturbances

Technology for caches

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Anatomy of an SRAM Cell

bit line b
bit line b word line

Stable Configurations
0 1 1 0

(6 transistors)

Terminology:

bit line: carries data word line: used for addressing

Write:

1. set bit lines to new data value b is set to the opposite of b 2. raise word line to high sets cell to new state (may involve flipping relative to old state)
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Read:

1. set bit lines high 2. set word line high 3. see which bit line goes low

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SRAM Cell Principle

Inverter Amplifies
Negative gain Slope < 1 in middle Saturates at ends Positive gain Slope > 1 in middle Saturates at ends

Inverter Pair Amplifies

1 0.9 0.8 0.7 0.6 0.5 0.4 0.3

V1 V2

Vin V2
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0.2

V1

0.1 0 0 0.2 0.4 0.6 0.8 1

Vin

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Bistable Element
Vin V2
1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.2 0.4 0.6 0.8 1
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Stability
V1
Require Vin = V2 Stable at endpoints recover from pertubation Metastable in middle Fall out when perturbed

Stable

Ball on Ramp Analogy

Metastable
Vin

V2

Stable

Vin

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Example SRAM Configuration (16 x 8)

W0 b7 b7 b1 b1 b0 b0

A0 A1 A2
A3

W1 Address decoder W15 memory cells

sense/write amps

sense/write amps

sense/write amps

R/W

Input/output lines d7
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d1

d0
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Dynamic RAM (DRAM)

Slower than SRAM
access time ~60 nsec

Nonpersistant
every row must be accessed every ~1 ms (refreshed)

Cheaper than SRAM

~$1.50 / MByte 1 transistor/bit

Fragile
electrical noise, light, radiation

Workhorse memory technology

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Anatomy of a DRAM Cell

Bit Line Word Line
Access Transistor

Storage Node Cnode

CBL

Writing
Word Line Bit Line Storage Node
V

Reading
Word Line Bit Line V ~ Cnode / CBL

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Addressing Arrays with Bits

Array Size
R rows, R = 2r C columns, C = 2c N = R * C bits of memory Addresses are n bits, where N = 2n row(address) = address / C leftmost r bits of address col(address) = address % C rightmost bits of address R = 2 C = 4 address = 6 address = r row n c col

Addressing

Example

0 1

0 000 100

1 001 101 row 1

2 010 110

3 011 111 col 2

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Example 2-Level Decode DRAM (64Kx1)

RAS 256 Rows 8 \ Row decoder

row A7-A0

Row address latch

256x256 cell array 256 Columns

col Provide 16-bit address in two 8-bit chunks

column sense/write amps

R/W

Column address latch

CAS

8 \

column latch and decoder

Dout Din

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DRAM Operation
Row Address (~50ns)
Set Row address on address lines & strobe RAS Entire row read & stored in column latches Contents of row of memory cells destroyed

Column Address (~10ns)

Set Column address on address lines & strobe CAS Access selected bit READ: transfer from selected column latch to Dout WRITE: Set selected column latch to Din

Rewrite (~30ns)
Write back entire row

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Observations About DRAMs

Timing
Access time (= 60ns) < cycle time (= 90ns) Need to rewrite row

Must Refresh Periodically

Perform complete memory cycle for each row Approximately once every 1ms Sqrt(n) cycles Handled in background by memory controller

Inefficient Way to Get a Single Bit

Effectively read entire row of Sqrt(n) bits

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Conventional Access Page Mode

Enhanced Performance DRAMs

RAS Row address latch row A7-A0 sense/write amps 8

Row + Col RAS CAS RAS CAS ... Row + Series of columns RAS CAS CAS CAS ... Gives successive bits

Row decoder

256x256 cell array

R/W

col Column address latch 8

Other Acronyms

EDORAM Extended data output CAS SDRAM Entire row buffered here Synchronous DRAM Typical Performance

column latch and decoder

row access time col access time cycle time 50ns 10ns 90ns
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page mode cycle time 25ns

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Video RAM
Performance Enhanced for Video / Graphics Operations Writing
Frame buffer to hold graphics image Random access of bits Also supports rectangle fill operations Set all bits in region to 0 or 1

256x256 cell array

Reading

Performance Example

Load entire row into shift register Shift out at video rates
1200 X 1800 pixels / frame 24 bits / pixel 60 frames / second 2.8 GBits / second
17

column sense/write amps

Shift Register

Video Stream Output

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DRAM Driving Forces

Capacity
4X per generation Square array of cells Typical scaling Lithography dimensions 0.7X Areal density 2X Cell function packing 1.5X Chip area 1.33X Scaling challenge Typically Cnode / CBL = 0.10.2 Must keep Cnode high as shrink cell size

Retention Time

Typically 16256 ms Want higher for low-power applications

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DRAM Storage Capacitor

Planar Capacitor
Up to 1Mb C decreases linearly with feature size

Trench Capacitor
4256 Mb Lining of hole in substrate

Plate Area A Dielectric Material Dielectric Constant d

Stacked Cell
> 1Gb On top of substrate Use high dielectric

C = A/d

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Trench Capacitor
Process
Etch deep hole in substrate Becomes reference plate Grow oxide on walls Dielectric Fill with polysilicon plug Tied to storage node

SiO2 Dielectric Storage Plate Reference Plate

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IBM DRAM Evolution

IBM J. R&D, Jan/Mar 95 Evolution from 4 256 Mb 256 Mb uses cell with area 0.6 m2 Cell Layouts

4 Mb Cell Structure

4Mb

16Mb

64Mb

256Mb

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Mitsubishi Stacked Cell DRAM

IEDM 95 Claim suitable for 1 4 Gb

Technology
0.14 m process Synchrotron X-ray source 8 nm gate oxide 0.29 m2 cell

Cross Section of 2 Cells

Storage Capacitor
Fabricated on top of everything else Rubidium electrodes High dielectric insulator 50X higher than SiO2 25 nm thick Cell capacitance 25 femtofarads

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Mitsubishi DRAM Pictures

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Magnetic Disks
Disk surface spins at 36007200 RPM

read/write head arm

The surface consists of a set of concentric magnetized rings called tracks

Each track is divided into sectors

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The read/write head floats over the disk surface and moves back and forth on an arm from track to track.
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Disk Capacity
Parameter
Number Platters Surfaces / Platter Number of tracks Number sectors / track Bytes / sector

18GB Example
12 2 6962 213 512

Total Bytes

18,221,948,928

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Disk Operation
Operation
Read or write complete sector

Seek
Position head over proper track Typically 6-9ms

Rotational Latency
Wait until desired sector passes under head Worst case: complete rotation 10,025 RPM 6 ms

Read or Write Bits

Transfer rate depends on # bits per track and rotational speed E.g., 213 * 512 bytes @10,025RPM = 18 MB/sec. Modern disks have external transfer rates of up to 80 MB/sec DRAM caches on disk help sustain these higher rates
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Disk Performance
Getting First Byte
Seek + Rotational latency = 7,000 19,000 sec

Getting Successive Bytes

~ 0.06 sec each roughly 100,000 times faster than getting the first byte!

Optimizing Performance:
Large block transfers are more efficient Try to do other things while waiting for first byte switch context to other computing task processor is interrupted when transfer completes

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Disk / System Interface

1. Processor Signals Controller
Read sector X and store starting at memory address Y (1) Initiate Sector Read

Processor
Reg

(3) Read Done

2. Read Occurs

Cache

Direct Memory Access (DMA) transfer Memory-I/O bus Under control of I/O controller (2) DMA Transfer I/O 3. I/O Controller controller Memory

Signals Completion

Interrupts processor Can resume suspended process

Disk

Dis k

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Magnetic Disk Technology

Seagate ST-12550N Barracuda 2 Disk
Linear density Bit spacing Track density Track spacing Total tracks Rotational Speed Avg Linear Speed Head Floating Height 52,187. 0.5 3,047. 8.3 2,707. 7200. 86.4 0.13 bits per inch (BPI) microns tracks per inch (TPI) microns tracks RPM kilometers / hour microns

Analogy:
put the Sears Tower on its side fly it around the world, 2.5cm above the ground each complete orbit of the earth takes 8 seconds

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CD Read Only Memory (CDROM)

Basis
Optical recording technology developed for audio CDs 74 minutes playing time 44,100 samples / second 2 X 16-bits / sample (Stereo) Raw bit rate = 172 KB / second Add extra 288 bytes of error correction for every 2048 bytes of data Cannot tolerate any errors in digital data, whereas OK for audio 172 * 2048 / (288 + 2048) = 150 KB / second For 1X CDROM N X CDROM gives bit rate of N * 150 E.g., 12X CDROM gives 1.76 MB / second 74 Minutes * 150 KB / second * 60 seconds / minute = 650 MB
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Bit Rate

Capacity

Storage Trends
metric 1980 1985 1990 1995 2000

2000:1980

SRAM

$/MB access (ns)

metric

19,200 300
1980

2,900 150
1985

320 35
1990

256 15
1995

100 2
2000

190 100
2000:1980

DRAM

$/MB 8,000 access (ns) 375 typical size(MB) 0.064

metric 1980

880 200 0.256

1985 100 75 10
31

100 100 4
1990 8 28 160

30 70 16
1995 0.30 10 1,000

1.5 60 64
2000 0.05 8 9,000

5,300 6 1,000
2000:1980 10,000 11 9,000

Disk

$/MB 500 access (ms) 87 typical size(MB) 1

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(Culled from back issues of Byte and PC Magazine)

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Storage Price: $/MByte

1.E+05 1.E+04

1.E+03

1.E+02

1.E+01

SRAM DRAM Disk

1.E+00

1.E-01

1.E-02

1980
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1985

1990
32

1995

2000
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Storage Access Times (nsec)

1.E+08 1.E+07 1.E+06

1.E+05 SRAM DRAM Disk

1.E+04 1.E+03

1.E+02 1.E+01

1.E+00

1980
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1985

1990
33

1995

2000
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Processor clock rates

Processors
metric 1980 1985 6 286 1990 20 386 1995 2000

2000:1980
600

typical clock(MHz) 1 processor 8080

150 600 Pentium P-III

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The CPU vs. DRAM Latency Gap (ns)

1.E+03

1.E+02 SRAM DRAM CPU cycle 1.E+01

1.E+00

1980
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1985

1990
35

1995

2000
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Memory Technology Summary

Cost and Density Improving at Enormous Rates Speed Lagging Processor Performance Memory Hierarchies Help Narrow the Gap:
Small fast SRAMS (cache) at upper levels Large slow DRAMS (main memory) at lower levels Incredibly large & slow disks to back it all up

Locality of Reference Makes It All Work

Keep most frequently accessed data in fastest memory

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