Jaeger/Blalock

7/1/03
Microelectronic Circuit Design
McGraw-Hill
Chapter 16
Analog Integrated Circuits
Microelectronic Circuit Design
Richard C. Jaeger
Travis N. Blalock
Chap 16 - 1
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Chapter Goals
Understand bipolar and MOS current mirror operation and mirror ratio errors.
Explore high output resistance current sources including cascode and Wilson
current sources.
Design current sources for both discrete and integrated applications.
Study reference current circuits such as V
BE
-based reference, bandgap
reference and Widlar current source.
Use current mirrors as active loads in differential amplifiers to increase
voltage gain of single-stage amplifiers.
Study effects of device mismatch on amplifier performance.
Analyze design of classic A741 op amp.
Study realization of four-quadrant analog multipliers with large input signal
range.
Increase understanding of SPICE simulation techniques.
Chap 16 - 2
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
MOS Current Mirrors: DC Analysis
MOSFETs M
1
and M
2
are
assumed to have identical V
TN
,
K
n
, , and W/L ratios.
I
REF
provides operating bias to
mirror.
V
DS1
= V
GS1
= V
GS2
=V
GS
) 1 (
1 DS1
V
n
K
REF
2I
TN
V
GS1
V
+
+ =
|
|
.
|

\
|
|
.
|

\
|
+ = =
DS2
V
TN
V
GS2
V
n
K
D2
I
O
I 1
2
2
( )
( )
REF
I
DS1
V
DS2
V
REF
I
O
I ~
+
+
=

1
1
However, due to mismatches, V
DS1
is
not equal to V
DS2
and there is slight
mismatch between output and
reference currents. Mirror ratio is:
( )
( )
DS1
V
DS2
V
REF
I
O
I

+
+
= =
1
1
MR
Chap 16 - 3
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
MOS Current Mirror (Example)
Problem:Calculate output current for given current mirror.
Given data: I
REF
= 150 A, V
SS
= 10 V, V
TN
= 1 V, K
n
= 250 A/V
2
, =
0.0133 V
-1
Analysis: (1+ V
DS1
) term is neglected to simplify dc bias calculation.
V 10 . 2
2
V
A
250
) A 150 ( 2
V 1
2
1 1
= + = + = =
n
K
REF
I
TN
V
GS
V
DS
V
A 165
V) 10 . 2 (
V
0133 . 0
1
V) 10 (
V
0133 . 0
1
) A 150 ( =
+
+
=
|
|
.
|

\
|
|
|
.
|

\
|
O
I
Actual currents are found to be mismatched by approximately 10%.
Chap 16 - 4
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
MOS Current Mirrors: Changing Mirror
Ratio
Mirror ratio can be changed by
modifying W/L ratios of the two
transistors forming the mirror.
1
1
|
|
.
|

\
|
=
L
W
'
n
K
n
K
2
2
|
|
.
|

\
|
=
L
W
'
n
K
n
K
( )
( )
( )
( )
DS1
V
L
W
DS2
V
L
W
REF
I
DS1
V
n1
K
DS2
V
n2
K
REF
I
O
I

+
+
=
+
+
=
|
|
.
|

\
|
|
|
.
|

\
|
1
1
1
2
1
1
( )
( )
DS1
V
L
W
DS2
V
L
W

+
+
=
|
|
.
|

\
|
|
|
.
|

\
|
1
1
1
2
MR
In given current mirror, I
o
=5I
REF
. Again
mismatch in V
DS
causes error in MR.
Chap 16 - 5
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Bipolar Current Mirrors: DC Analysis
BJTs Q
1
and Q
2
are assumed to
have identical I
S
, V
A
, |
FO
, and
W/L ratios.
I
o
= I
C2
, I
REF
= I
C1
+ I
B1
+
I
B2

V
BE1
= V
BE2
=V
BE
( )
|
.
|

\
|
+ +
+
=
FO A
V
CE2
V
A
V
CE2
V
REF
I
O
I
|
2
1
) / ( 1
Finite current gain of BJT causes slight
mismatch between I
o
and I
REF
.
) / 2 ( 1
1
MR
FO REF
I
O
I
| +
= =
|
|
|
|
|
.
|

\
|
|
|
|
.
|

\
|
+ =
A
V
CE
V
T
V
BE
V
S
I
C
I
1
1 exp
1
|
|
|
|
|
.
|

\
|
|
|
|
.
|

\
|
+ =
A
V
CE
V
T
V
BE
V
S
I
C
I
2
1 exp
2
|
|
|
|
|
.
|

\
|
+ =
A
V
CE
V
FO F
1
1
1
| |
|
|
|
|
|
.
|

\
|
+ =
A
V
CE
V
FO F
2
1
2
| |
|
|
|
.
|

\
|
=
T
V
BE
V
FO
S
I
B
I exp
1
|
|
|
|
.
|

\
|
=
T
V
BE
V
FO
S
I
B
I exp
1
|
Chap 16 - 6
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Current Mirror (Example)
Problem:Calculate and compare mirror ratios for BJT and MOS current
mirror.
Given data: I
REF
= 150 A, V
GS
= 2 V, V
DS2
= V
CE2
= 10 V, = 0.02 V
-1
V
A
= 50 V, |
FO
= 100, V
SS
= 10 V, M
1
= M
2
, Q
1
= Q
2
.

Analysis:
( )
( )
15 . 1
1
1
MOS
MR =
+
+
=
DS1
V
DS2
V

( )
16 . 1
2
1
) / ( 1
BJT
MR =
+ +
+
=
|
.
|

\
|
FO A
V
CE2
V
A
V
CE2
V
|
Chap 16 - 7
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Bipolar Current Mirrors: Changing Mirror
Ratio
Mirror ratio can be changed by
modifying the emitter area of the
transistor.
A
E
A
SO
I
S
I =
Emitter area scaling changes the
transport equations using which,



Ideally, MR= n, but for finite gain,
( )
|
.
|

\
|
+
+ +
+
=
FO
n
A
V
CE2
V
A
V
CE2
V
REF
nI
O
I
|
1
1
) / ( 1
E1
A
E2
A
n =
FO
n
1
n
|
+
= MR
Chap 16 - 8
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Multiple Current Sources
Reference current enters diode-
connected transistor M
1
establishing
gate-source voltage to bias M
2
through
M
5
, each with different W/L ratio.
Absence of current gain defect permits
large number of MOSFETs to be
driven by one reference transistor.
Similar multiple bipolar sources can
be built from one reference BJT.
As base current error term worsens
when more BJTs are added, umber of
outputs of basic bipolar mirror are
limited.
Chap 16 - 9
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Buffered Bipolar Current Mirror
When large mirror ratio is used or
if many source currents are
generated from one reference BJT,
current gain defect worsens.
Current gain of Q
3
is used to
reduce base current that is
subtracted from reference current.
Assuming infinite Early voltage for simplicity,
( )
FO3
FO1
C
I
n
REF
I
B3
I
REF
I
C1
I
|
|
+
+
= =
1
1
) 1 (
) 1 (
) 1 (
1
1
FO3 FO1
n
REF
nI
C1
I n
O
I
| | +
+
+
= =
Thus error term in denominator is
reduced.
Chap 16 - 10
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Output Resistance of Current Mirrors
For diode connected BJT, from
small-signal model,
m
g
R
g
o
g
m
g
1
i
v
v ) ( i
~ =
+ + =
t
...If |
o
and
F
>>1
This simplifies the ac model of
the current mirror. Similar
analysis applies to MOSFET
current mirror except that the
current gain is infinite. Thus

or
A2
V
CS
V
o
r
out
R
~
=
2
2
CS
V

1
=
Chap 16 - 11
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Two-port Model for Current Mirror
Since current mirror has a
current input and current
output, we use h-parameters.
2
v
22 1
i
21 2
i
2
v
12 1
i
11 1
v
h h
h h
+ =
+ =
n
m
g
m
g
r
m
g
r
m
g
h
m
g g
m
g
h
= ~
+
=
=
=
~
+
=
=
=
1
2
2 1
1
2 2
0
2
v
1
i
2
i
21
1
1
2 1
1
0
2
v
1
i
1
v
11
t
t
t
For MOS current mirrors,
0
0
1
i
2
v
1
v
12
=
=
= h
2
1
0
1
i
2
v
2
i
22
o
r
h =
=
=
1
1
11
m
g
h =
0
12
= h
n
m
g
m
g
h ~ ~
1
2
21
2
1
22
o
r
h =
Chap 16 - 12
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Bipolar Widlar Current Source
R in Widlar source allows
adjustment of mirror ratio.
|
|
|
|
|
.
|

\
|
|
|
|
|
|
.
|

\
|
~ + =
1
ln
1
1 ln
1
S
I
REF
I
T
V
S
I
REF
I
T
V
BE
V
|
|
|
|
|
.
|

\
|
|
|
|
|
|
.
|

\
|
~ + =
2
ln
2
1 ln
2
S
I
O
I
T
V
S
I
O
I
T
V
BE
V
Current through R is given by:

If transistors are matched,






Typically 1 < K < 10.
|
|
|
|
|
.
|

\
|
=

=
1
2
ln
2 1
2
S
I
S
I
O
I
REF
I
R
T
V
R
BE
V
BE
V
E
I
|
|
|
|
|
.
|

\
|
= =
1
2
ln
2
E
A
E
A
O
I
REF
I
R
T
V
E
I
F O
I o
A2
V K
CS
V
o
Kr
S
I
S
I
O
I
REF
I
o
r
R
m
g
o
r
out
R
~
=
|
|
.
|

\
|
+ =
+ ~
|
|
|
|
|
.
|

\
|
|
|
.
|

\
|
2
1
2
ln 1
2
2
1
2
Chap 16 - 13
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
PTAT Voltage
Voltage developed across R in Widlar current source is directly
proportional to absolute temperature.





Example: T = 300 K, I
C1
= I
C2
and A
E2
= 10 A
E1
. Then =59.6 mV with
temperature coefficient of slightly< +0.2 mV/K
PTAT voltage combined with A-D converter is the core of electronic
thermometers.
T
V
E
A
E
A
C
I
C
I
q
k
T
V
E
A
E
A
C
I
C
I
q
kT
E
A
E
A
C
I
C
I
T
V
BE
V
BE
V V
PTAT
1
2
2
1
ln
PTAT
1
2
2
1
ln
1
2
2
1
ln
2 1 PTAT
+ = + =
c
c
= = =
|
|
|
|
|
.
|

\
|
|
|
|
|
|
.
|

\
|
|
|
|
|
|
.
|

\
|
Chap 16 - 14
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
MOS Widlar Current Source
If I
O
is known, I
REF
can be directly
calculated. If I
REF
, R and W/L ratios are
known, we can write a quadratic
equation in terms of
Small-signal model for MOS Widlar
source represents a C-S stage with
resistor R in its source.
Current through R is given by:
|
|
|
|
.
|

\
|
=

=
2
) / (
1
) / (
1
1
2
1
2
2
1
2
2 1
L W
L W
REF
I
O
I
n
K
REF
I
R
R
n
K
O
I
n
K
REF
I
R
GS
V
GS
V
O
I
|
|
|
|
.
|

\
|
=
2
) / (
1
) / (
1
1
2
1
L W
L W
REF
I
O
I
n
K
REF
I
R
REF
I
O
I
|
|
.
|

\
|
+ = R
m
g
o
r
out
R
2
1
2
REF
I
O
I /
Chap 16 - 15
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
MOS Wilson Current Source
During operation, all
transistors are in active
region. I
D2
= I
REF
, I
D3
= I
D1

= I
O
, V
GS3
= V
GS1
=V
GS

( )
( )
GS
V
GS
V
D
I
D2
I

+
+
=
1
2 1
1
( )
( )
GS
V
GS
V
REF
I
O
I

+
+
=
1
2 1
1
2
n
K
REF
I
TN
V
GS
V + =
where
1
v
3
gs
v
3
x
i
1
v
3
v
x
v
+ =
+ =
|
|
.
|

\
|
o
r
m
g
From small-signal model,
3 2
2
1
2
2 3
x
i
x
v
o
r
f
f
f o
r
out
R

~ + + ~ =
|
|
|
|
.
|

\
|
)
1
v
2
(
1
x
i
1
v
2
v
gs
v
f
m
g
= =
3
2

f
CS
V ~
Chap 16 - 16
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Bipolar Wilson Current Source
During operation, all transistors are
in active region. But some current is
lost at base of Q
3
and current gain
error is formed by Q
1
and Q
2
.
I
REF
= I
C2
+ I
B3

V
CE1
= V
BE
V
CE2
= 2V
BE
2
3 3 o
r
o
out
R
|
~
2
A
V
o
CS
V
|
~
( )
|
.
|

\
|
+
+
+
+
=
A
V
BE
2V
FO FO
A
V
BE
V
REF
I
O
I
) 2 (
2
1
) / ( 1
| |
Addition of extra BJT can balance the
circuit and reduce errors due to mismatch.
V
CE2
= V
BE
+V
BE3
-V
BE4
= V
BE

Chap 16 - 17
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
MOS Cascode Current Source
I
D1
= I
D3
= I
REF
Also I
O
= I
D4
= I
D2
. So current
mirror forces output current to be approximately
equal to the reference current. If all transistors are
matched with equal W/L ratios,
V
DS2
= V
GS1
+ V
GS3
-V
GS4
= V
GS
= V
DS1




From the small-signal model,
2 4 2 4
1
4 o
r
f o
r
m
g
o
r
out
R ~ + =
|
|
.
|

\
|
4
4
2
4

f f
CS
V ~ ~
Chap 16 - 18
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Bipolar Cascode Current Source
I
C1
= I
C3
= I
REF
Also I
O
= I
C4
= I
C2
. So current
mirror forces output current to be approximately
equal to the reference current. If all transistors are
matched,
V
CE2
= V
BE1
+ V
BE3
-V
BE4
= V
GS
= V
CE1




From the small-signal model,
2
4 4 o
r
o
out
R
|
~
2
4 4 A
V
o
CS
V
|
~
Chap 16 - 19
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Electronic Current Source Design
Example
Problem: Design IC current source to meet given specifications.
Given data: I
REF
= 25 A, V
SS
= 20 V, = 0.02 V
-1
,

V
TN
= 0.75 V, K
n
= 50
A/V
2
,

V
A
= 50 V, |
FO
= 100, I
SO
= 0.5 fA
Analysis: MR <0.1 % requires output current of 25 A25 nA when output
voltage is 20 V. Choose 1GO for safety margin.

Cascode or Wilson sources voltage-balanced MOS version must be used to
meet this value of V
CS
and for small MR. We can choose cascode source as
it doesnt involve internal feedback loop.W/L ratios are all same as MR=1.

Using
f
=500, =0.02/V and I
D
=25 A gives value of K
n
=1.25 mS. Since
K
n
= K
n
(W/L) we need a W/L ratio of 25/1 for given technology.
O = > M 800
nA 25
V 20
out
R
25,000V ) A(1G 25 = O =
CS
V
D
I
D
I
n
K
o
r
m
g
CS
V
f

1
2 500 V 000 , 25
V
02 . 0
~ = = = = |
.
|

\
|
Chap 16 - 20
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Reference Current Generation
Reference current is required by all current mirrors.
When resistor is used, sources output current is directly
proportional to V
EE
.

Gate-source voltages of MOSFETs can be large and
several MOS devices can be connected in series between
supplies to eliminate large resistors.
V
DD
+ V
SS
= V
SG4
+ V
GS3
+ V
GS1
and I
D3
= I
D1
= I
4
Change in supply directly alters gate-source voltage of
MOSFETs and the reference current.
BJTs cant similarly be connected in series due to small
fixed voltage developed across each diode and
exponential relation between voltage and current.
R
BE
V
EE
V
REF
I

=
Chap 16 - 21
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Supply-Independent Biasing: JFET
Constant Reference Current Source

P-channel JFETs can be used to set a
fixed reference current.
JFET is operating with V
SG
=0 and thus
I
D
= I
DSS
, assuming that V
SD
is large
enough to pinch-off the JFET.
Depletion-mode MOSFETs can be used
in similar manner.
Since both these methods require special
IC processes, other methods are
preferred.
Chap 16 - 22
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Supply-Independent Biasing: V
BE
-based
Reference and Widlar Current Source
Output current is determined by
base-emitter voltage of Q
1
. For
high current gain,
1
V 4 . 1
1
2 1
1
R
EE
V
R
BE
V
BE
V
EE
V
C
I

~

=
1 1
V 4 . 1
ln
2
2
V 7 . 0
2
1
1
2
1
2 2 2
R
S
I
EE
V
R
T
V
O
I
R
R
BE
V
B
I
R
BE
V
F E
I
F O
I

~
~ ~ + = =
|
|
|
|
|
.
|

\
|
o o
Output current is now logarithmically
dependent on supply voltage. However, it is
temperature dependent due to temperature
coefficients of both V
BE
and R.
Widlar source also achieves similar supply
independence of output current.
|
|
|
|
|
.
|

\
|
= =
1
2
ln
2
E
A
E
A
O
I
REF
I
R
T
V
E
I
F O
I o
Chap 16 - 23
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Supply-Independent Biasing: Bias Cell
Using Widlar Source and Current Mirror
Assuming high current gain, pnp
current mirror forces I
C1
= I
C2
.
Emitter area ratio for Widlar
source is shown to be 20.
R R
T
V
C
I
V 0749 . 0
20 ln
1
= = |
.
|

\
|
Actual value of output current depends on temperature
and absolute value of R. I
C1
= I
C2
=0 is also a stable
operating point and start-up circuits must be included
in IC realizations to ensure that circuit reaches desires
operating point.
Base-emitter voltages of Q
1
and Q
4
can be used as
reference voltages for other current mirrors.
In MOS analog of the circuit, I
D3
= I
D4
and so
I
D1
= I
D2
.



|
|
|
|
.
|

\
|
=
2
) / (
1
) / (
1
1 2
2
L W
L W
n
K
D
I
R
Chap 16 - 24
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Variation of Reference Cell Current with
Power Supply Fluctuations
R is absorbed into transistor model in
simplified small-signal circuit model.
EE
V
CC
V
x
v A + A =
or
SS
V
DD
V
x
v A + A =
2
v '
2 1
v ) '
2 1
(
x
i
o
g
m
g
m
g + + =
)
2
v
x
v (
4
i =
m
g Using


Determinant of these nodal equations is:
2
v
4
x
v )
3 1
(
x
v )
3 4
(
m
ng
o
g
m
g
o
g
m
ng + + = +
2
v
4
x
v )
3 1
(
x
v )
3 4
(
m
ng
o
g
m
g
o
g
m
ng + + = +
2
)v '
2 4
(
1
v '
2
x
v
4 o
g
m
g
m
g
m
g + + =
3
2
1
'
2
1
4 1
(
(
(
(

(
(
(
(
(

+ = A
F
m
g
O
m
g
m
g
n -
m
g
m
g

Chap 16 - 25
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Variation of Reference Cell Current with
Power Supply Fluctuations (contd.)
A
(
(
(

+ + =
|
|
|
|
|
|
.
|

\
|
x
v
) '
2 3
(
4
1
v
f
o
g
m
g
O
o
ng
m
g
m
g

A
(
(
(

+
|
|
.
|

\
|
=
|
|
|
|
|
|
.
|

\
|
x
v
2
1
'
2
1
4 1
2
v
f
m
g
O
m
g
m
g
n
m
g
m
g

|
|
.
|

\
|

+
+
= =
|
|
|
|
|
|
|
|
|
|
.
|

\
|
1
'
2
1
1
'
2
1
'
2
1
3
x
i
x
v
m
g
m
g
n
n
o
r
m
g
m
g
o
r
out
R
1
1
'
2
<
m
g
m
g
n
for .This is important
for stability. Because of positive
feedback, overall output resistance
is reduced.
Output resistances of the Widlar source and current mirror, r
o2
and r
o3
determine sensitivity to power supply variations. To improve output resistance
of Widlar portion , cascode sources can be used and Wilson sources can be
used to improve output resistance of current mirror.
Chap 16 - 26
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Reference Current Design Example
Problem: Design supply-independent current source to meet given
specifications.
Given data: output current

= 45 A,T=300 K, total current< 60 A V
CC
=
V
EE
= 5 V,

V
A
= 75 V, |
FO
= 100, I
SO
= 0.1 fA, V
T
= 25.88 mV
Analysis:




Also . Choose I
C2
=5 I
C1
. Then A
E2
/ A
E1
<28.45 Choosing
A
E2
/A
E1
=20,
Finally, A
E1
=A, A
E2
=20 A, A
E3
=A, A
E4
=5 A with 35.88 mV across R.
69 . 5
1
2
2
1
739 . 1
25.88mV
1k A 45
2
1
2
2
1
ln
s
=
O
s =
|
.
|

\
|
|
.
|

\
|
|
|
|
|
|
.
|

\
|
E
A
E
A
C
I
C
I
T
V
R
C
I
E
A
E
A
C
I
C
I
3
A 15
A 45
1
2
= >
C
I
C
I
O =
O
=
|
.
|

\
|
|
.
|

\
|
797
A 45
1k A 45 4) 25.88mVln(
R
Chap 16 - 27
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Bandgap Reference
To make the voltage reference
temperature independent,
negative temperature coefficient
of base-emitter junction can be
canceled by positive
temperature coefficient of
scaled PTAT voltage.
PTAT
GV
BE
V
BG
V + =

To have zero temperature coefficient,





V
GO
is silicon bandgap voltage at 0K (1.12
V)
BE
V
T
V
GO
V
PTAT
GV
T
PTAT
V
G
T
T
V
GO
V
BE
V
T
PTAT
V
G
T
BE
V
T
BG
V
+ =
= +

=
c
c
+
c
c
=
c
c
3
0
3
T
V
GO
V
BG
V 3 + =
Chap 16 - 28
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Bandgap Reference Circuit Realization
1
2
ln
1
2
2
1
E
A
E
A
T
V
R
R
BE
V
BG
V + =
PTAT
V
BE
V
T
V
GO
V
T
PTAT
V
T
BE
V
R
R
2
3
1
2
1
1
2
+
=
c
c
c
c
=
Circuit gain G =2 R
2
/ R
1
.
Voltages other than
1.2 V can be obtained
by a adding resistive
voltage divider.
BG
V
R
R
O
V
|
|
|
|
|
.
|

\
|
+ =
3
4
1
Chap 16 - 29
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Bandgap Reference Example
Problem: Design bandgap reference to meet given specifications.
Given data: V
O
= 5 V,T=320 K, collector current

= 25 A, I
S
= 0.5 fA.
Assumptions: V
A
is infinite, |
FO
is infinite, A
E2
=10 A
E1
, drop across R =2 V.
Analysis:
O = = =
= =
=
|
|
|
|
|
.
|

\
|
k 539 . 2
A 25
mV 47 . 63
PTAT
1
mV 47 . 63 mV)ln(10) 57 . 27 (
1
2
2
1
ln
PTAT

E
I
V
R
E
A
E
A
C
I
C
I
q
kT
V
V 6792 . 0
1
1
ln
T BE1
= =
|
|
|
|
|
.
|

\
|
S
I
C
I
V V
124 . 4
2
3
1
2
=
+
=
PTAT
V
BE
V
T
V
GO
V
R
R
O = = k 47 . 10
1
124 . 4
2
R R
V 203 . 1
1
2
2
1
= + =
PTAT
V
R
R
BE
V
BG
V
157 . 3 1
3
4
= =
BG
V
O
V
R
R
k 24
3
3
= =
I
BG
V
R
k 9 . 75
3
4
=

=
I
BG
V
O
V
R
O = = k 80
A 25
V 2

R
Chap 16 - 30
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
CMOS Differential Amplifier with
Active Load: DC Analysis
I
D3
= I
D1
= I
D2
=I
D4
=I
DSS
/2.
Mirror ratio is set by M
3
and M
4
and is exactly
unity when V
SD4
= V
SD3
and thus V
SD1
= V
SD2
.
Differential amplifier is completely balanced at
dc when:
|
|
|
|
|
.
|

\
|
= =
TP
V
p
K
SS
I
DD
V
SD
V
DD
V
O
V
4
TP
V
p
K
SS
I
SG
V
SD
V
DD
V
p
K
SS
I
n
K
SS
I
TP
V
TN
V
DD
V
DS
V
= =
~ + + + =
3 3
1
Chap 16 - 31
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
CMOS Differential Amplifier with Active
Load: Differential-Mode Signal Analysis
The differential amplifier can be
represented by its Norton equivalent.
Total short circuit output current:
id
v
2
2
id
v
2
2
o
i
m
g
m
g
= =
Thevenin equivalent output resistance:

Differential-mode voltage gain:
4
2
o
r
o
r
th
R =
2
2
4 2
f
o
r
o
r
m2
g
th
R
sc
i
dm
A

~ = =
|
|
.
|

\
|
Chap 16 - 32
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
CMOS Differential Amplifier with
Active Load: Output Resistance
Assume R
SS
>>1/ g
m1
.
Resistance looking into drain of
M
2
(C-G transistor) is:
2
2
1
1
2
1
2 2
1
2 o
r
m
g
m
g
o
r
S
R
m
g
o
r
o2
R = + = + =
|
|
|
|
|
.
|

\
|
|
|
.
|

\
|
Drain current of M
2
(v
x
/2r
o2
)is replicated by
current mirror as drain current of M
4
. Total
current from source is 2(v
x
/2r
o2
)= v
x
/r
o2
.
Total current is:


Output resistance is:
4
x
v
2
x
v
i
T
x
o
r
o
r
+ =
4
2
o
r
o
r
od
R =
Chap 16 - 33
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
CMOS Differential Amplifier with Active
Load: Common-Mode Signal Analysis
From small-signal equivalent:





where it is assumed that g
m4
= g
m3
and G
oc
<< g
m3
.
Also
ss
R
ic
v
oc
i
2
~
2
2
o
r
od
R =
SS
R
f
oc
R 2 =
oc
G
o
g
o
g
m
g
oc
i
3
v
+ + +

=
|
|
.
|

\
|
2 /
2 3 3
|
|
|
|
|
.
|

\
|
|
|
|
|
|
.
|

\
|
|
|
|
.
|

\
|
+
~ + =
SS
R
ic
v
f
o
r
o
r
v
o
g
v
m
g
oc
i
sc
i
2
3
2
3
1
3
2
2
3 4

|
|
.
|

\
|
|
|
|
|
|
.
|

\
|
+
= =
4 2
3
2
2
3
1
o
r
o
r
SS
R
f
o
r
o
r
ic
v
th
R
sc
i
cm
A

Chap 16 - 34
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
CMOS Differential Amplifier with Active
Load: CMRR and Mismatch Contribution
SS
R
m
g
f
o
r
o
r
SS
R
m
g
f
cm
A
dm
A
2 3
2
/
3
1
2 3
2
CMRR

~
+
= =
|
|
.
|

\
|
for r
o3
= r
o2
.
With mismatched transistors, assuming
v
d1
=0 and gate-source voltages are equal,

With v
gs
= v
ic
- v
s
, v
d1
=0 and v
d2
=0,
s
v
o
g
gs
v
m
g
d
i
d
i
sc
i A A = =
2 1
ic
v
ic
v
SS
R
m
g
SS
R
m
g
s
v ~
+
~
2 1
2
ic
v
f SS
R
m
g
ic
v
SS
R
m
g
SS
R
o
g
gs
v
|
|
|
|
|
|
.
|

\
|
+ ~
+
+
~

1
2
1
2 1
2 1
( )
(
(
(
(
(
(

|
|
|
.
|

\
|
+
A
= = =
f
o
g
o
g
f SS
R
m
g
m
g
m
g
o
r
o
r
m
g
cm
A
dm
A
cm
A

1 1
2
1
4 2
1 -
CMRR
Chap 16 - 35
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Bipolar Differential Amplifier with
Active Load: DC Analysis
I
C3
= I
C1
= I
C2
=I
C4
=I
EE
/2.
If |
FO
is very large, current
mirror ratio is set by Q
3
and
Q
4
and is exactly 1 when V
EC4

= V
EC3
=V
EB
.

EB
V
CC
V
O
V =
CC
V
BE
V
EB
V
CC
V
E
V
C
V
CE
V
CE
V ~ = = = ) ( ) (
2 1
Differential amplifier is completely balanced at dc when:


Current gain defect in current mirror upsets dc balance.
As longs as BJTs are in forward-active region, V
EC4

adjusts to make up for current-gain defect.

As I
C2
=I
C4
and I
C2

=I
C1
, MR must be
1.
( )
|
.
|

\
|
+ +
+
=
FO4 A
V
CE
V
A
V
CE4
V
C1
I
C4
I
|
2
1
) / ( 1
FO4
A
V
EB
V
EC4
V
|
2
+ =
This causes an equivalent
input offset voltage of
dd
A
EB
V
EC4
V
dd
A
EC3
V
EC4
V
OS
V

=

=
Chap 16 - 36
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Bipolar Differential Amplifier with Active
Load: Differential-Mode Signal Analysis
To eliminate offset error, buffered
current mirror active load is used.
Total short circuit output current:
id
v
2
2
id
v
2
2
sc
i
m
g
m
g
= =
Thevenin equivalent
output resistance:

Differential-mode voltage gain:
4
2
o
r
o
r
th
R =
( )
L
R
m2
g
L
R
o
r
o
r
m2
g
dm
v
th
R
L
R
sc
i
dm
A = = =
|
|
.
|

\
|
4 2
With added stages,
output resistance of
differential input
stage is:
5
5 4
2 t
t
r r
o
r
o
r
eq
R ~ =
5
/
2 5
2
C
I
C
I
o
eq
R
m
g
dm
A
| =
=
Chap 16 - 37
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Bipolar Differential Amplifier with Active
Load: Common-Mode Signal Analysis





|
|
|
.
|

\
|
= =
o
r
o
EE
R ic
v
C
R
ic
v
cc
A
oc
i
|
1
2
1
|
|
|
.
|

\
|
|
|
|
.
|

\
|
~ =
EE
R
o
r
o
f2
ic
v
o
r
m
g
EE
R
o
r
o
ic
v
sc
i
2
1 1
)
2
2 (
3
1
2
1 1
2
|

|
From small-signal equivalent:
1
2
2
1
2
1
3
2
/
2
CMRR

|
|
|
.
|

\
|
~ =
|
|
|
|
|
|
.
|

\
|
EE
R
m
g
f
o
o ic
v
th
R
sc
i
th
R
m
g
| |
|
|
|
.
|

\
|
=
EE
R
o
r
o
o
ic
v
sc
i
2
1 1
2
|
|
Current forced in differential output resistance
is doubled due to current mirror action.




Due to mismatches,
(
(
(
(
(
(

|
|
|
|
.
|

\
|
A

|
|
|
.
|

\
|
+
A
+
A
=
f
o
g
o
g
f SS
R
m
g g
g
m
g
m
g

t
t
1 1
2
1
1 -
CMRR
Chap 16 - 38
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Active Loads in Op Amps: Voltage Gain
2
5
)
5
2
(
2
))
10
(
5
(
5 2
2
2
)
4
2
(
2 1
f
o
r
o
r
m
g
o
r
GG
R
o
r
m
g
vt
A
f
o
r
o
r
m
g
vt
A

= ~ + =
~ =
4
5 2
2 1
) 1 (
2 1
b
v
o
v
a
v
b
v
id
v
a
v
f f
vt
A
vt
A
vt
A
vt
A
dm
A

=
~ = =
Gain of output stage is approximately 1.
If Wilson stage is used in first-stage active
load, A
vt1
=
f2
. If current source M
10
is
replaced by a Wilson or cascode source,
A
vt2
=
f5
.Overall gain can be raised to:
5 2 f f dm
A =
Chap 16 - 39
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Active Loads in Op Amps: DC Design
Considerations
When op amp with active load is
operated in closed-loop configuration,
I
D5
= I
2
, the output current of source
M
10
.
For minimum offset voltage, (W/L)
5

must be such that V
SG5
= V
SD4
= V
SG3

precisely sets I
D5
= I
2
and accounts for
V
DS
and differences between M
5
and
M
10
.
R
GG
, (W/L)
6
and (W/L)
7
determine
quiescent current in class-AB output
stage.
V
GS11
can be used to bias output stage
in place of R
GG
.
Chap 16 - 40
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
CMOS Op Amp Analysis
Problem: Find small-signal characteristics of given CMOS op amp.
Given data: I
REF
= 100 A, V
DD
= V
SS
= 5 V, V
TN
= 1 V, V
TP
= -0.75 V,
K
n
= 25 A/V
2
, K
p
= 10 A/V
2
, = 0.0125 V
-1
Analysis:
A 100
1 2
= = =
REF
I /2 I
D
I
A 200 2
2 5
= = =
REF
I I
D
I
000 , 16
5
5
2
5
1
2
2
2
2
1
4
1
4
5 2
= =
=
|
|
|
|
|
.
|

\
|
|
|
|
|
|
.
|

\
|
D
I
p
K
D
I
n
K
f f
dm
A


= =
ic
R
id
R
V 54 . 2
11
11
2
11 11
= + =
n
K
D
I
TN
V
GS
V
As I
D6
= I
D7
, V
GS6
= V
SG7
= V
GS11
/2
A 7 . 33
2
) V 75 . 0 V 27 . 1 (
2
V
A
2
250
6 7
=
= =
D
I
D
I
S
4
10 3 . 1
6 7

= =
m
g
m
g
O = = k 85 . 3
7
1
6
1
m
g
m
g
out
R
Chap 16 - 41
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Bipolar Op Amps
Q
1
to Q
4
form differential input
stage with active load.
First stage is followed by high-
gain C-E amplifier, Q
5
and its
current source load, Q
8
.
Load resistance is driven by class-
AB output stage formed by Q
6
and
Q
7
, biased by I
2
and diodes Q
11

and Q
12
.

2
5
5
5
2
2
5
5 5 5
5
2
) 1 ( ) 1
6
(
8 5 2 5 2
3 2 1
f
o
C
I
C
I
o
r
m
g r
m
g
m
g
m
g
L
R
o o
r
o
r
m
g r
m
g
vt
A
vt
A
vt
A
dm
A

|
t
|
t
= ~
+ ~
=
|
|
|
.
|

\
|
|
|
.
|

\
|
|
|
.
|

\
|
Chap 16 - 42
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Bipolar Op Amps with Improved
Voltage Gain
To improve gain, 2-transistor Darlington circuit
with current gain of |
o1
|
o2
, amplification factor

f2
/4, output resistance r
o2
/2 and input
resistance 2|
o1
r
t2
,is used to replace Q
5
. It
requires emitter-base bias of 2V
EB
.
Buffered current mirror maintains dc
balance at collectors of Q
3
and Q
4
.
2
7
)
14
3
7
2
(
2
7
2
2
23 . 0 )
7 6
2
2
2
(
2 1
f
o
r
o
r
m
g
vt
A
f
r
o
o
r
m
g
vt
A

t
|
= ~
~ =
Using I
2
=2 I
1
, |
o
=50, V
A
=60 V,
V
CE
= 15 V,
5
10 15 . 4
22
7 2
3 2 1
= =
=
f f
vt
A
vt
A
vt
A
dm
A

Chap 16 - 43
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Input Stage Breakdown in Bipolar Op
Amps
Input stage of bipolar op amp has no
overvoltage protection and can easily be
destroyed by large input voltage
differences due to fault conditions or
unavoidable transients, such as slew-rate
limited recovery.
In worst-case fault condition, B-E junction
of Q
1
is forward-biased and that of Q
2
is
reverse-biased by(V
CC
+ V
EE
- V
BE1
). If V
CC

= V
EE
=22 V, reverse voltage > 41 V.
Early IC op amps used external
diode protection across input
terminals to limit differential input
voltage to about 1.4 V at the cost of
extra components.

Chap 16 - 44
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
A741 Op Amp
High gain, input resistance and
CMRR, low output resistance
and good frequency response.
Fully protected input and output
stages and offset adjustment port.
Input stage is a differential
amplifier with buffered current
mirror active load.
Two stages of voltage gain
(emitter-follower driving C-E
amplifier) followed by short-
circuit protected class-AB output
stage buffered from second gain
stage by emitter follower.
Chap 16 - 45
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
A741 Op Amp: Bias Circuitry
mA 733 . 0
5
2
=
+
=
R
BE
V
EE
V
CC
V
REF
I
|
|
|
|
|
.
|

\
|
=
1
ln
5000
1
I
REF
I
T
V
I
Solving iteratively,
I
1
=18.4 A.
Assuming V
O
=0, V
CC
=15 V and neglecting drop
across R
7
and R
8
,
V
EC23
= 15+1.4=16.4 V and V
EC24
= 15-0.7 =14.3 V
Given V
A
=60 V, |
FO
=50,
A 666
) 50 / 2 ( ) 60 / 7 . 0 ( 1
) 60 / 4 . 16 ( 1
mA) 733 . 0 ( 75 . 0
2
=
+ +
+
= I
A 216
) 50 / 2 ( ) 60 / 7 . 0 ( 1
) 60 / 4 . 14 ( 1
mA) 733 . 0 ( 25 . 0
3
=
+ +
+
= I
O =
+
=
+
= k 115
mA 666 . 0
16.4V V 60
2
23 23
2
I
EC
V
A
V
R
O =
+
=
+
= k 344
mA 216 . 0
14.3V V 60
3
24 24
3
I
EC
V
A
V
R
Chap 16 - 46
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
A741 Op Amp:DC Analysis of Input
Stage
/2 I
C
I
1 6 1
~

4
2
)
8
/
8
( )
8
/ 2 ( 1
)
8
/
8
( 1
2
2
1 B
I
A
V
EB
V
FO
A
V
EC
V
C
I I +
+ +
+
=
|
4
1
4
1
2
2
2 2 2 B
I
FO
FO
FO
E
I
F C
I
|
|
.
|

\
|
+
+
= = |
|
|
o
(
(
(
(
(
(
(
(
(
(

+
~
4
1
8
2
8
8 8
1
1
2
1
2
FO FO A
V
EB
V
EC
V
I
C
I
| |
2
1
4
4
2
1
2
4 4 4 C
I
FO
FO
FO
FO
E
I
F C
I
+
+
= =
|
|
|
|
o
CC
V
BE
V
EB
V
CC
V
CE
V
CE
V ~ + = =
2 9 2 1
V 1 . 2
V) 4 . 1 (- - V 7 . 0
3 3 3
=
+ = =
EE
V
EE
V
C
V
E
V
EC
V
V 7 . 0
7
V 4 . 1
8
=
+ =
EE
V
CE
V
CC
V
EC
V
Chap 16 - 47
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
A741 Op Amp: Input Stage Bias
Currents Example
Problem: Calculate bias currents in the 741 input stage with given parameters.
Given data: I
1
= 18 A,V
CC
= V
EE
= 15 V,

V
Anpn
= 75 V, |
FOnpn
= 150, V
Apnp
= 60
V, |
FOpnp
= 60
Analysis:
A 32 . 7
) 1 60 )( 151 / 150 (
1
) 60 / 7 . 0 ( ) 50 / 2 ( 1
) 60 / 4 . 16 ( 1
1
2
A 18
2 1
V 4 . 16
3 1 8

=
+
+
+ +
+
= =
~ + + =
C
I
C
I
EB
V
BE
V
CC
V
EC
V
A 25 . 7
3 5
A 25 . 7
2
151
150
61
60
2
1
4
4
2
1
2
2
2
4 4 4 4 3 6

|
|
|
|
o
o o
= ~
= =
+
+
= = = = =
|
|
|
.
|

\
|
|
|
|
|
|
.
|

\
|
C
I
C
I
C
I
C
I
FO
FO
FO
FO
F
C
I
F E
I
F C
I
C
I
C
I
Chap 16 - 48
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
A741 Op Amp: AC Analysis of Input
Stage
Using symmetry of the input stage differential-
mode half circuit can be drawn.
2
4
id
v
1
4
4
) 1
2
(
2
2 /
id
v
4
) 1
2
(
2
2 /
id
v
b
i
b
i
2 b
i ) 1
2
(
4
e
i
4
o
i
t
|
t
|
t
|
t
| | o o
r
o
r
o
r
in
R
o
r
o o o o
~
+
+ +
=
+ +
=
~ + = =
|
|
|
|
|
.
|

\
|
id
v
4
2
2
4
id
v
2
o
i
m
g
r
o
= ~
t
|
2
4
b
i
id
v
id t
r R = =
4
2
4
1
4 o
r R
m
g
o
r
out
R = + ~
|
|
.
|

\
|
Chap 16 - 49
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
A741 Op Amp: Voltage Gain (Input
Stage)
id
S)v
4
10 46 . 1 (
id
v
2
20
2
id
v
2
- i 2
o
i

=
= = =
C
I
m
g
( )
O = = =
+ ~ =
M 54 . 6
4
79 . 0
4
2
6
3 . 1
4
2
2 6
1
6 4
6
o
r
o
r
o
r
o
r R
m
g
o
r
out
R
out
R
th
R
Based on values in Norton equivalent, open-
circuit voltage gain of first stage is -955.
Chap 16 - 50
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
A741 Op Amp: Voltage Gain (Second
Stage)
k 189
10
10
10
A 8 . 19
k 50
11
11
11
10 10
= =
= + = ~
C
I
o
r
B
V
F
C
I
E
I
C
I
|
t

|
k 63 . 5
11
=
t
r
To find y
11
and y
21
:
O = O + +
O = + + =
|
|
.
|

\
|
|
|
.
|

\
|
=
(

|
|
.
|

\
|

.4M 2
11
k 50 1
10 10 11
k 7 . 20 100 1
11 11 11
1
in
R
o
r y
o
r
in
R
|
t
|
t
( )( )
( )( )
1
v 921 . 0
11
k 50 1
10 10
11
k 50 1
10
1
v
e
v =
O + +
O +
=
in
R
o
r
in
R
o
|
t
|
1
v 006701 . 0
100 )
11
/ 1 (
e
v
2
i =
O +
=
m
g
mS 70 . 6
21
= y
Chap 16 - 51
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
A741 Op Amp: Voltage Gain (Second
Stage contd.)
To find y
12
and y
22
:





Open-circuit voltage gain for the first two
stages is:
O =
O = + =
|
|
.
|

\
|
=
(

|
|
.
|

\
|

k 1 . 89
11 2
22
k 407 100
11
1
11 11
1
out
R R y
E
R
m
g
o
r
out
R
id
v 000 , 153 )
id
v 256 ( 597
2
v
id
v 256
id
v 2.4M 6.54M
4
10 46 . 1
1
v
1
v 597
1
v ) k 1 . 89 ( 00670 . 0
2
v
= =
= O O

=
= O =
|
.
|

\
|
Combined model for first and
second stages is:
Chap 16 - 52
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
A741 Op Amp: Voltage Gain (Output
Stage)
From simplified output stage without
short-circuit protection:
O = + + =
O = + + =
O = + + =
|
|
.
|

\
|
|
|
.
|

\
|
M 27 . 8
1
1
12 12 12
k 162
2
3
13 14 1
k 304 1
15 15 2
eq
R
o
r
in
R
eq
R R
d
r
d
r
eq
R
L
R
o
r
eq
R
|
t
|
t
O =
+
+
=
O =
+

+
+ + =
|
|
|
|
|
.
|

\
|
2 . 26
1
15
3 15
k 08 . 2
1
12
1
22 12
13 14
3 3
o
eq
R r
o
R
o
y r
d
r
d
r R
eq
R
|
t
|
t
Actual op amp output resistance is:
O = + = 53
7
R
o
R
out
R
Chap 16 - 53
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Gilbert Analog Multiplier
Q
1
and Q
2
have significant emitter
degeneration, transconductance of
the pair is 1/ R
1
.For v
1
< R
1
I
BB
,
|
|
|
.
|

\
|
|
|
|
|
|
.
|

\
|
|
|
|
.
|

\
|
|
|
.
|

\
|
|
|
.
|

\
|
= =
+ =
+ + =
T
V
v
R
R
v
T
V
v
R
C
i
C
i
R
C
i
C
i
C
i
C
i
R
C
i
C
i
C
i
C
i
o
v
2
2
tanh
1
1 2
2
tanh )
2 1
(
)
6 5
( )
4 3
(
)
6 4
( )
5 3
(
Multiplication can be achieved by expanding
the tanh as a series and keeping only first
term.


But this restricts input signal range of v
2
to
only a few tens of mV.



...
2
3
) tanh( + =
x
x x
|
|
|
.
|

\
|
|
|
|
|
|
.
|

\
|
~
T
V
v
R
R
v
o
v
2
2
tanh
1
1
Chap 16 - 54
Jaeger/Blalock
7/1/03
Microelectronic Circuit Design
McGraw-Hill
Four-Quadrant Gilbert Analog Multiplier
with Predistortion Circuit
For v
3
< R
3
I
EE
,
3 1
3 1
3
3 1
tanh 2
3
3
1
3
3
1
tanh
8
tanh
7
tanh
10 9
)
9
( )
10
(
2
v v
R R
EE
I
R
o
v
R
EE
I
v
T
V
R
EE
I
v
R
EE
I
v
T
V
S
I
C
i
T
V
S
I
C
i
T
V
BE
v
BE
v
BE
v
BB
V
BE
v
BB
V v
|
|
|
|
|
.
|

\
|
|
|
|
|
|
.
|

\
|
|
|
|
|
|
|
|
|
|
.
|

\
|
|
|
|
|
|
.
|

\
|
|
|
|
|
|
.
|

\
|
=

+
= =
= =
3
2
3
2 7 R
v
EE
I
C
i + ~
3
2
3
2 8 R
v
EE
I
C
i ~
Chap 16 - 55