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Low Power Vlsi Design1

This document discusses trends in low power VLSI design. It outlines sources of power consumption in CMOS chips, including dynamic, short circuit, and static power dissipation. Techniques for reducing power consumption are discussed at the system, architectural, logic gate, circuit, and physical levels. The document emphasizes that reducing power consumption is an important challenge as integration densities and operating frequencies continue to increase with advances in semiconductor technology.

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Shruthi Gourishetti
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© Attribution Non-Commercial (BY-NC)
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Download as PPTX, PDF, TXT or read online on Scribd
242 views

Low Power Vlsi Design1

This document discusses trends in low power VLSI design. It outlines sources of power consumption in CMOS chips, including dynamic, short circuit, and static power dissipation. Techniques for reducing power consumption are discussed at the system, architectural, logic gate, circuit, and physical levels. The document emphasizes that reducing power consumption is an important challenge as integration densities and operating frequencies continue to increase with advances in semiconductor technology.

Uploaded by

Shruthi Gourishetti
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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TRENDS IN LOW POWER VLSI DESIGN

Under the Guidance of Ms.P.Anitha

G.Shruthi (12N31D6811)

OUTLINE
Importance of Low Power VLSI Design Sources of Power Consumption in CMOS Power Consumption Considerations Optimization Metrics Techniques for Power Reduction Conclusion

ROAD MAP FOR FEATURE SIZE OF TRANSISTORS

IMPORTANCE OF LOW POWER VLSI DESIGN


The potential increase in packing densities as the feature size of the MOS devices shrinks. Logic density for the Intel microprocessors doubles every process generation. The frequency of operation has dramatically increased due to the device scaling Introduction of performance boosting techniques, such as pipelining, and parallel architectures.

SOURCES OF POWER CONSUMPTION IN CMOS

Dynamic Power Dissipation Short Circuit Power Dissipation Static Power Dissipation

DYNAMIC POWER DISSIPATION


The Dynamic power dissipation is the power required for the circuit to perform its anticipated tasks. Dynamic Power dominates the total power consumption.

Pdynamic = CL * Vdd Vdd *

DYNAMIC POWER DISSIPATION

SHORT CIRCUIT POWER DISSIPATION


Direct current from Vdd to GND when both transistors on. In this PMOS and NMOS devices are simultaneously Conducting.

Pshort circuit = Isc * Vdd

STATIC POWER DISSIPATION


The Static power is when input is not switching. In static power dissipation is very small and can be ignored.

Pstatic = Istatic * Vdd

POWER CONSUMPTION CONSIDERATIONS

Supply Voltage level


Device Threshold Voltage Physical capacitance Switching Frequency

OPTIMIZATION METRICS
Performance degradation is acceptable to a given bound that is represented by performance or timing constraints. Thus, power minimization requires optimal exploitation of the slack on performance constraints. Besides power versus performance, another key trade-off in VLSI design involves power versus flexibility Power minimization

TECHNIQUES FOR POWER REDUCTION


System Level Architectural level Logic Gate Level Circuit Level Physical level

SYSTEM LEVEL
System level is the highest level of abstraction It consist of Hardware infrastructure executing software programs Hardware Platform consist of Execution unit Storage Unit Communication interface Network Software consist of application &system software

ARCHITECTURAL LEVEL
Architectural level is the structural view of data path and logical view of control Unit. It consist of parallelism and pipelining Exploitation In this level when the supply voltage is less the performance is reduced by half.

LOGIC GATE LEVEL


The RTL or Behavioral design is transformed into a logic gate level using predefined technology. In this technique we are using CAD tools Path equalization Technique

CIRCUIT LEVEL
The low power cell design lies at the heart of the circuit level technique to reduce the power consumption. In this technique we consider transistor sizing circuit design style

POWER CONSUMPTION REDUCTION AT


CIRCUIT LEVEL

POWER CONSUMPTION REDUCTION AT CIRCUIT LEVEL CONTD.

POWER CONSUMPTION REDUCTION AT CIRCUIT LEVEL CONTD.

CONCLUSION

advances in technology and fabrication, the integration ensities and the rate at which chips operate have increased drastically, causing power consumption to be of primary concern. In addition, the new requirements set by device portability, reliability, and costs have helped in alleviating the power consumption threat in CMOS circuits. Because the power problem is getting more concerning, very largescale integrated circuit (VLSI) designers need to develop new efficient techniques to reduce the power dissipation in current and future technologies, a task that is full of challenges but yet exciting to explore.

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