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Dynamic RAM

Dynamic RAM (DRAM) uses a capacitor and transistor in each memory cell to store bits of data as electrical charges. The capacitor leaks charge over time, so the memory controller must refresh all cells periodically by reading and rewriting the data to recharge the capacitors before they fully discharge. This refresh operation is required for dynamic RAM to retain the stored data and is the source of its name.

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Kiran Kumar Parlapalli
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299 views

Dynamic RAM

Dynamic RAM (DRAM) uses a capacitor and transistor in each memory cell to store bits of data as electrical charges. The capacitor leaks charge over time, so the memory controller must refresh all cells periodically by reading and rewriting the data to recharge the capacitors before they fully discharge. This refresh operation is required for dynamic RAM to retain the stored data and is the source of its name.

Uploaded by

Kiran Kumar Parlapalli
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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10.

3 Dynamic RAM(1)
10.3.1 Introduction

Random access memory (RAM) is the best known form of computer memory. RAM is considered "random access" because you can access any memory cell directly if you know the row and column that intersect at that cell.
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10.3 Dynamic RAM(2)


10.2.2 DRAM

In the most common form of computer memory, dynamic random access memory (DRAM), a transistor and a capacitor are paired to create a memory cell, which represents a single bit of data. The capacitor holds the bit of information -a 0 or a 1. The transistor acts as a switch that lets the control circuitry on the memory chip read the capacitor or change its state.
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10.3 Dynamic RAM(3)

A capacitor is like a small bucket that is able to store electrons. To store a 1 in the memory cell, the bucket is filled with electrons. To store a 0, it is emptied. The problem with the capacitor's bucket is that it has a leak. In a matter of a few milliseconds a full bucket becomes empty. Therefore, for dynamic memory to work, either the CPU or the memory controller has to come along and recharge all of the capacitors holding a 1 before they discharge. To do this, the memory controller reads the memory and then writes it right back. This refresh operation happens automatically thousands of times per second.

10.3 Dynamic RAM(4)

The capacitor in a dynamic RAM memory cell is like a leaky bucket. It needs to be refreshed periodically or it will discharge to 0.

10.3 Dynamic RAM(5)


This refresh operation is where dynamic RAM gets its name. Dynamic RAM has to be dynamically refreshed all of the time or it forgets what it is holding. The downside of all of this refreshing is that it takes time and slows down the memory.
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Memory cells are etched onto a silicon wafer in an array of columns (bitlines) and rows (wordlines). The intersection of a bitline and wordline constitutes the address of the memory cell.

10.3 Dynamic RAM(6)


Column Address Strobe

Memory is made up of bits arranged in a twodimensional grid. In this figure, red cells represent 1s and white cells represent 0s.

10.3 Dynamic RAM(7)


DRAM works by sending a charge through the appropriate column (CAS) to activate the transistor at each bit in the column. When writing, the row lines contain the state the capacitor should take on. When reading, the sense-amplifier determines the level of charge in the capacitor. If it is more than 50 percent, it reads it as a 1; otherwise it reads it as a 0. The counter tracks the refresh sequence based on which rows have been accessed in what order. The length of time necessary to do all this is so short that it is expressed in nanoseconds (billionths of a second). A memory chip rating of 70ns means that it takes 70 nanoseconds to completely read and recharge each cell. Return Back

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