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Nano Scale Devices For Low Power VLSI Design

This document discusses CMOS scaling trends and their effects on power dissipation. As technology scales down, leakage power becomes a major component of total power. Gate leakage increases significantly for sub-65nm technologies and is dependent on process variations. Techniques like dual oxide thickness and dual gate doping can help reduce gate leakage while maintaining performance. Further research is still needed to address gate leakage estimation and reduction during circuit design and synthesis.

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Er Paramjit Singh
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74 views

Nano Scale Devices For Low Power VLSI Design

This document discusses CMOS scaling trends and their effects on power dissipation. As technology scales down, leakage power becomes a major component of total power. Gate leakage increases significantly for sub-65nm technologies and is dependent on process variations. Techniques like dual oxide thickness and dual gate doping can help reduce gate leakage while maintaining performance. Further research is still needed to address gate leakage estimation and reduction during circuit design and synthesis.

Uploaded by

Er Paramjit Singh
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Nano scale devices for low power VLSI Design by

SANJEEV SHARMA

Outline of the Talk


Introduction CMOS scaling Trends and Effects Power consumption redistribution due to scaling Components of Power Dissipation Components of Leakage Gate leakage analysis Gate leakage variation with process and design parameters Gate leakage reduction

Introduction
The demand for power sensitive designs has grown significantly due to the fast growth of battery-operated portable applications. As the technology scaling continues unabated, subthreshold device design has gained a lot of attention due to the low power and ultra-low-power consumption in various applications. Design of low-power high-performance submicron and deep submicron CMOS devices and circuits is a big challenge. Short-channel effect is a major challenge for scaling the gate length down and below 0.1 m.

Cont.
MetalOxide-SemiconductorField-Effect-transistor (MOSFET) has been the major device for integrated circuits over the past two decades. The process parameters in low power design are 1 Channel length(L) 2 Oxide thickness(Tox) 3 Threshold voltage(Vth), and 4 Doping concentration in the channel.

Cont
As the technology is scaled down, process parameter variations have become severe problem for low-power design. The low-power design technique should be such that it is less sensitive to the process parameter variations.

CMOS Driven Applications

Almost the entire industry today is driven by CMOS

Scaling Trend Transistor Count

Increase in Transistor Count per chip

Scaling Trend Frequency

With scaling the transistors are becoming twice as fast as the previous generation

What is Physically Scaled ? (Gate Length and Gate thickness)

Gate length of the transistor has been decreasing with technology scaling. All the other dimensions including gate oxide thickness have been scaled down to support this trend

Other Parameters Scaled?

Scaling Trend Power Dissipation


Power dissipated by the transistor has manifested itself most emphatically along with scaling. The power density is increasing exponentially

Power Dissipation Components in CMOS

Problems of Power Dissipation

Continuously increasing performance demands

Increasing power dissipation of technical devices


Today: power dissipation is a main problem High Power dissipation leads to:

High efforts for cooling Reduced time of operation Higher weight (batteries) Reduced mobility Increasing operational costs Reduced reliability

Leakages in Nanoscale CMOS

I1: reverse bias pn junction (both ON & OFF) I2: subthreshold leakage (OFF ) I3:oxide tunneling current (both ON & OFF) I4: gate current due to hot carrier injection (both ON & OFF) I5: gate induced drain leakage (OFF) I6: channel punch through current (OFF)

Power Dissipation : Redistribution

Scaling Trends and Effects : Summary



Scaling improves Transistor Density of chip Functionality on a chip Speed and frequency of operation Higher performance
Scaling and power dissipation Active power remains almost constant Components of leakage power increase in number and in magnitude. Gate leakage (tunneling) predominates for sub 65-nm technology.

Gate Leakage Components

Gate oxide tunneling current components in BSIM4.4.0 model. Igs, Igd: Components due to the overlap of gate and diffusions Igcs, Igcd: Components due to tunneling from the gate to the diffusions via the channel and Igb: Component due to tunneling from the gate to the bulk via the channel.

Note: all the currents are with respect to gate.GBSDIgs-IgdIgcsIgcdIgb

Gate Leakage Estimation


Gate leakage is input state dependent Gate leakage is dependent on position of ON/OFF transistors Gate leakage is sensitive to process variation Gate leakage estimation methods for logic level description of the circuit: Pattern dependent estimation Pattern independent probabilistic estimation

Techniques for Gate Leakage Reduction


Research in Gate leakage is catching up and have not matured like that of dynamic or subthreshold power. Few methods: Dual TOX Dual K Gate oxide tunneling current Ioxide (k is a experimentally derived factors): Dual K Technique: Basis Use of multiple dielectrics (denoted as Kgate) of multiple thickness (denoted as Tgate) will reduce the gate tunneling current significantly while maintaining the performance.

Conclusions and Future Research


Gate leakage is an major component of power consumption in nano-scale CMOS circuits. Gate leakage is present in both ON and OFF state of a MOS device. Few research works so far have addressed its estimation in CMOS circuits. Few research works address its reduction in CMOS circuit. Use of high-K is expected to be a stable solution for the gate leakage problem, which is largely unaddressed from modeling and synthesis flow point of view.

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