Digital Logic Circuits

Introduction

DIGITAL LOGIC CIRCUITS

Logic Gates

Boolean Algebra
Map Specification Combinational Circuits

Flip-Flops
Sequential Circuits Memory Components Integrated Circuits

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Digital Logic Circuits

Logic Gates

LOGIC GATES
Digital Computers - Imply that the computer deals with digital information, i.e., it deals with the information that is represented by binary digits - Why BINARY ? instead of Decimal or other number system ? * Consider electronic signal 1
7 6 5 signal 4 3 range 2 1 0

0 binary * Consider the calculation cost - Add 0 1 0 0 1 1 1 10

octal
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 1011 3 4 5 6 7 8 9 101112 4 5 6 7 8 9 10111213 5 6 7 8 9 1011121314 6 7 8 9 101112131415 7 8 9 10111213141516 8 9 1011121314151617 9 101112131415161718

0 1 2 3 4 5 6 7 8 9

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Logic Gates

BASIC LOGIC BLOCK - GATE Binary Digital Input Signal Binary Digital Output Signal

. . .

Gate

Types of Basic Logic Blocks

- Combinational Logic Block Logic Blocks whose output logic value depends only on the input logic values

- Sequential Logic Block Logic Blocks whose output logic value depends on the input values and the state (stored information) of the blocks
Functions of Gates can be described by - Truth Table - Boolean Function - Karnaugh Map
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Logic Gates

COMBINATIONAL GATES
Name
A

Symbol
X B A X B

Function
X=AB or X = AB

Truth Table
A 0 0 1 1 A 0 0 1 1 B 0 1 0 1 B 0 1 0 1 A 0 1 A 0 1 B 0 1 0 1 B 0 1 0 1 B 0 1 0 1 B 0 1 0 1 X 0 0 0 1 X 0 1 1 1 X 1 0 X 0 1 X 1 1 1 0 X 1 0 0 0 X 0 1 1 0 X 1 0 0 1

AND OR I Buffer NAND NOR XOR

Exclusive OR

X=A+B

A A A B A B A B A B

X X

X=A X=A A 0 0 1 1 A 0 0 1 1 A 0 0 1 1 A 0 0 1 1

X = (AB)

X = (A + B) X=AB or X = AB + AB X = (A B) or X = AB+ AB

XNOR
Exclusive NOR or Equivalence

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Digital Logic Circuits

Boolean Algebra

BOOLEAN ALGEBRA
Boolean Algebra * Algebra with Binary(Boolean) Variable and Logic Operations * Boolean Algebra is useful in Analysis and Synthesis of Digital Logic Circuits - Input and Output signals can be represented by Boolean Variables, and - Function of the Digital Logic Circuits can be represented by Logic Operations, i.e., Boolean Function(s) - From a Boolean function, a logic diagram can be constructed using AND, OR, and I Truth Table * The most elementary specification of the function of a Digital Logic Circuit is the Truth Table

- Table that describes the Output Values for all the combinations of the Input Values, called MINTERMS - n input variables --> 2n minterms
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Digital Logic Circuits

Boolean Algebra

LOGIC CIRCUIT DESIGN

x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 F 0 1 0 0 1 1 1 1

Truth Table

Boolean Function

F = x + yz

Logic Diagram

x y z

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Boolean Algebra

BASIC IDENTITIES OF BOOLEAN ALGEBRA

[1] x + 0 = x [3] x + 1 = 1 [5] x + x = x [7] x + x = 1 [9] x + y = y + x [11] x + (y + z) = (x + y) + z [13] x(y + z) = xy +xz [15] (x + y) = xy [17] (x) = x [2] x 0 = 0 [4] x 1 = x [6] x x = x [8] x X = 0 [10] xy = yx [12] x(yz) = (xy)z [14] x + yz = (x + y)(x + z) [16] (xy) = x + y
[15] and [16] : De Morgans Theorem

Usefulness of this Table - Simplification of the Boolean function - Derivation of equivalent Boolean functions to obtain logic diagrams utilizing different logic gates -- Ordinarily ANDs, ORs, and Inverters -- But a certain different form of Boolean function may be convenient to obtain circuits with NANDs or NORs --> Applications of DeMorgans Theorem xy = (x + y) I, AND --> NOR x+ y= (xy) I, OR --> NAND

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Boolean Algebra

EQUIVALENT CIRCUITS
Many different logic diagrams are possible for a given Function

F = ABC + ABC + AC = AB(C + C) + AC = AB 1 + AC = AB + AC

(1)
A B C

....... (1) [13] ... (2) [7] [4] .... (3)

(2)

A B C F

(3)

A B C

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Boolean Algebra

COMPLEMENT OF FUNCTIONS
A Boolean function of a digital logic circuit is represented by only using logical variables and AND, OR, and Invert operators. --> Complement of a Boolean function - Replace all the variables and subexpressions in the parentheses appearing in the function expression with their respective complements A,B,...,Z,a,b,...,z A,B,...,Z,a,b,...,z (p + q) (p + q) - Replace all the operators with their respective complementary operators AND OR OR AND - Basically, extensive applications of the DeMorgans theorem

(x1 + x2 + ... + xn ) x1x2... xn

(x1x2 ... xn)' x1' + x2' +...+ xn'
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Map Simplification

SIMPLIFICATION
Truth Table Unique Simplification from Boolean function - Finding an equivalent expression that is least expensive to implement - For a simple function, it is possible to obtain a simple expression for low cost implementation - But, with complex functions, it is a very difficult task Karnaugh Map(K-map) is a simple procedure for simplifying Boolean expressions. Truth Table Karnaugh Map Boolean function
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Boolean Function Many different expressions exist

Simplified Boolean Function

Digital Logic Circuits

Map Simplification

KARNAUGH MAP
Karnaugh Map for an n-input digital logic circuit (n-variable sum-of-products form of Boolean Function, or Truth Table) is - Rectangle divided into 2n cells - Each cell is associated with a Minterm - An output(function) value for each input value associated with a mintern is written in the cell representing the minterm --> 1-cell, 0-cell Each Minterm is identified by a decimal number whose binary representation is identical to the binary interpretation of the input values of the minterm. x 0 1
Identification of the cell

x 0 1

F 1 0

0 1

Karnaugh Map value x of F 0 0 1 1 F(x) = (1)

x 0 0 1 1

y 0 1 0 1

F 0 1 1 1

y0 1 x 0 0 1 1 2 3

1-cell
y0 1 x 0 0 1 1 1 0 F(x,y) = (1,2)
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Map Simplification

KARNAUGH MAP
x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 F 0 1 1 0 1 0 0 0

y yz x 00 01 11 10 0 0 1 3 2 x 1 4 5 7 6 z

yz x 00 01 11 10 0 0 1 0 1 1 1 0 0 0

F(x,y,z) = (1,2,4)

u 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

v 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

w 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

x 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

F 0 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0

w wx uv 00 01 11 10 00 0 1 3 2 v 01 4 5 7 6 12 13 15 14 u 11 10 8 9 11 10 x wx uv 00 01 11 10 00 0 1 1 0 01 0 0 0 1 11 0 0 0 1 10 1 1 1 0 F(u,v,w,x) = (1,3,6,8,9,11,14)

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Map Simplification

MAP SIMPLIFICATION - 2 ADJACENT CELLS Rule: xy +xy = x(y+y) = x Adjacent cells - binary identifications are different in one bit --> minterms associated with the adjacent cells have one variable complemented each other Cells (1,0) and (1,1) are adjacent Minterms for (1,0) and (1,1) are x y --> x=1, y=0 x y --> x=1, y=1

F = xy+ xy can be reduced to F = x From the map y x 0 1 0 0 0

1 1 1 F(x,y) = (2,3) = xy+ xy =x
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2 adjacent cells xy and xy --> merge them to a larger cell x

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Map Simplification

MAP SIMPLIFICATION - MORE THAN 2 CELLS uvwx + uvwx + uvwx + uvwx = uvw(x+x) + uvw(x+x) = uvw + uvw = uv(w+w) = uv uv wx wx ux w w uv uv 1 1 1 1 1 1 1 1 vw 1 1 1 1 v v 1 1 1 1 u u 1 1 1 1 uw x x vx

uvwx+uvwx+uvwx+uvwx+uvwx+uvwx+uvwx+uvwx = uvw(x+x) + uvw(x+x) + uvw(x+x) + uvw(x+x) = u(v+v)w + u(v+v)w = (u+u)w = w wx w w V uv uv 1 1 1 1 1 1 w 1 1 v v 1 1 u u 1 1 1 1 u 1 1 1 1 1 1 x x

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Map Simplification

MAP SIMPLIFICATION
wx uv 00 00 1 01 0 11 0 10 0 01 1 0 1 1 11 10 0 1 0 0 1 0 0 0 w 1 1 0 0 0 1 0 1 0 1 0 0 1 0 0 0 v

(0,1), (0,2), (0,4), (0,8)

Adjacent Cells of 1 Adjacent Cells of 0

(1,0), (1,3), (1,5), (1,9)

x F(u,v,w,x) = (0,1,2,9,13,15) Merge (0,1) and (0,2)

--> uvw + uvx

Merge (1,9)
--> vwx

... ... Adjacent Cells of 15

(15,7), (15,11), (15,13), (15,14)

Merge (9,13)
--> uwx

Merge (13,15)
--> uvx

F = uvw + uvx + vwx + uwx + uvx But (9,13) is covered by (1,9) and (13,15) F = uvw + uvx + vwx + uvx
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Digital Logic Circuits

Map Simplification

IMPLEMENTATION OF K-MAPS - Sum-of-Products Form Logic function represented by a Karnaugh map can be implemented in the form of I-AND-OR A cell or a collection of the adjacent 1-cells can be realized by an AND gate, with some inversion of the input variables. y x y z

1
x z

1
1

x y z x y z

x z

F(x,y,z) = (0,2,6)

1 1

y z

x y z x y z x y z

x z y z I AND OR

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Map Simplification

IMPLEMENTATION OF K-MAPS - Product-of-Sums Form Logic function represented by a Karnaugh map can be implemented in the form of I-OR-AND

If we implement a Karnaugh map using 0-cells, the complement of F, i.e., F, can be obtained. Thus, by complementing F using DeMorgans theorem F can be obtained
F(x,y,z) = (0,2,6) x x y y 1 0 0 1 0 0 0 1 z z

F = xy + z
F = (xy)z = (x + y)z

x y z I
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F OR AND
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Map Simplification

IMPLEMENTATION OF K-MAPS - Dont-Care Conditions In some logic circuits, the output responses for some input conditions are dont care whether they are 1 or 0. In K-maps, dont-care conditions are represented by ds in the corresponding cells. Dont-care conditions are useful in minimizing the logic functions using K-map. - Can be considered either 1 or 0 - Thus increases the chances of merging cells into the larger cells --> Reduce the number of variables in the product terms y x 1 d d 1 d 1 x yz z x y z
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Combinational Logic Circuits

COMBINATIONAL LOGIC CIRCUITS

Half Adder x 0 0 1 1 cn-1 cn 0 0 1 0 0 0 1 1 0 0 1 1 0 1 1 1 y 0 1 0 1 s 0 1 1 0 1 0 0 1 c 0 0 0 1 s 0 1 1 0 y 0 0 x 0 1 c = xy y
0 0 0 1

y 0 1 x 1 0 s = xy + xy =x y y
1 0 c n-1 1 0

x y

c s

Full Adder x y 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 x y cn-1

1 0

1 c n-1 1 1

0 1

cn

cn = xy + xcn-1+ ycn-1 = xy + (x y)cn-1 s = xycn-1+xycn-1+xycn-1+xycn-1 = x y cn-1 = (x y) cn-1

S

cn
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Digital Logic Circuits

Combinational Logic Circuits

COMBINATIONAL LOGIC CIRCUITS

Other Combinational Circuits

Multiplexer Encoder Decoder Parity Checker Parity Generator etc

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Combinational Logic Circuits

MULTIPLEXER
4-to-1 Multiplexer Select S1 S0 0 0 0 1 1 0 1 1 Output Y I0 I1 I2 I3

I0
I1 I2 I3 Y

S0 S1
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Combinational Logic Circuits

ENCODER/DECODER
Octal-to-Binary Encoder D1 D2 D3 D4 D5 D6 D7 A0

A1 A2

2-to-4 Decoder E 0 0 0 0 1 A1 0 0 1 1 d A0 0 1 0 1 d D0 0 1 1 1 1 D1 1 0 1 1 1 D2 1 1 0 1 1 D3 1 1 1 0 1 A0

D0 D1 D2 A1 E

D3

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Sequential Circuits

SEQUENTIAL CIRCUITS - Registers

A0 Q Clock I0 I1 I2
D C

A1 Q
D C

A2 Q
D C

A3 Q
D C

Shift Registers
Serial Input Clock D Q C D Q C D Q C

I3 Serial Output

D Q C

Bidirectional Shift Register with Parallel Load

A0 Q
D C

A1 Q
D C

A2
Q
D C

A3 Q
D C

4x1 MUX

4x1 MUX

4x1 MUX

4x1 MUX

Clock

S0S1 SeriaI I0
Input

I1

I2

Serial I3 Input
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Memory Components

MEMORY COMPONENTS
0 Logical Organization words (byte, or n bytes)

Random Access Memory

N-1

- Each word has a unique address - Access to a word requires the same time independent of the location of the word - Organization
k address lines Read Write

n data input lines

2k Words (n bits/word)

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Digital Logic Circuits

Memory Components

READ ONLY MEMORY(ROM)

Characteristics - Perform read operation only, write operation is not possible - Information stored in a ROM is made permanent during production, and cannot be changed - Organization k address input lines
m x n ROM (m=2k) n data output lines

Information on the data output line depends only on the information on the address input lines. --> Combinational Logic Circuit address
X0=AB + BC X1=ABC + ABC X2=BC + ABC X3=ABC + AB X4=AB ABC

Output X0 X1 X2 X3 X4

Canonical minterms Computer Organization

X0=ABC + ABC + ABC X1=ABC + ABC X2=ABC + ABC + ABC X3=ABC + ABC + ABC X4=ABC + ABC

000 001 010 011 100 101 110 111

1 1 0 0 0 1 0 0

0 1 1 0 0 0 0 0

0 0 0 1 1 0 0 1

0 0 1 0 1 1 0 0

0 0 0 0 0 0 1 1

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Memory Components

TYPES OF ROM
ROM - Store information (function) during production - Mask is used in the production process - Unalterable - Low cost for large quantity production --> used in the final products PROM (Programmable ROM) - Store info electrically using PROM programmer at the users site - Unalterable - Higher cost than ROM -> used in the system development phase -> Can be used in small quantity system EPROM (Erasable PROM) - Store info electrically using PROM programmer at the users site - Stored info is erasable (alterable) using UV light (electrically in some devices) and rewriteable - Higher cost than PROM but reusable --> used in the system development phase. Not used in the system production due to erasability

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Memory Components

INTEGRATED CIRCUITS
Classification by the Circuit Density SSI MSI LSI VLSI several (less than 10) independent gates 10 to 200 gates; Perform elementary digital functions; Decoder, adder, register, parity checker, etc 200 to few thousand gates; Digital subsystem Processor, memory, etc Thousands of gates; Digital system Microprocessor, memory module

Classification by Technology TTL Transistor-Transistor Logic Bipolar transistors NAND ECL Emitter-coupled Logic Bipolar transistor NOR MOS - Metal-Oxide Semiconductor Unipolar transistor High density CMOS - Complementary MOS Low power consumption
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