UNIT II 8051 MICROCONTROLLER

Contents:
Introduction Block Diagram and Pin Description of the 8051 Registers Memory mapping in 8051 Stack in the 8051 I/O Port Programming Timer Interrupt

Necessary tools for Microprocessor/controller

CPU: Central Processing Unit I/O: Input /Output Bus: Address bus & Data bus Memory: RAM & ROM Timer Interrupt Serial Port Parallel Port

Microprocessors:
General-purpose microprocessor
CPU for Computers No RAM, ROM, I/O on CPU chip itself ExampleIntels x86, Motorolas 680x0
Many chips on mothers board

CPU GeneralPurpose Microprocessor

Data Bus

RAM

ROM

I/O Port

Timer

Serial COM Port

Address Bus General-Purpose Microprocessor System

Microcontroller :

A smaller computer On-chip RAM, ROM, I/O ports... ExampleMotorolas 6811, Intels 8051, Zilogs Z8 and PIC 16X

CPU

RAM ROM

A single chip
I/O Port
Serial Timer COM Port Microcontroller

Microprocessor vs. Microcontroller

Microprocessor CPU is stand-alone, RAM, ROM, I/O, timer are separate designer can decide on the amount of ROM, RAM and I/O ports. expansive versatility general-purpose Microcontroller CPU, RAM, ROM, I/O and timer are all on a single chip fix amount of on-chip ROM, RAM, I/O ports for applications in which cost, power and space are critical single-purpose

Block Diagram
External interrupts Interrupt Control On-chip ROM for program code
Timer/Counter

On-chip RAM

Timer 1 Timer 0

Counter Inputs

CPU
Serial Port

OSC

Bus Control

4 I/O Ports

P0 P1 P2 P3

TxD RxD

Address/Data

Pin Description of the 8051

P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST (RXD)P3.0 (TXD)P3.1 (INT0)P3.2 (INT1)P3.3 (T0)P3.4 (T1)P3.5 (WR)P3.6 (RD)P3.7 XTAL2 XTAL1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Vcc P0.0(AD0) P0.1(AD1) P0.2(AD2) P0.3(AD3) P0.4(AD4) P0.5(AD5) P0.6(AD6) P0.7(AD7) EA/VPP ALE/PROG PSEN P2.7(A15) P2.6(A14) P2.5(A13) P2.4(A12) P2.3(A11) P2.2(A10) P2.1(A9) P2.0(A8)

8051 (8031)

Registers
A B R0 R1 R2 R3 R4 R5 R6 Some 8051 16-bit Register PC PC DPTR DPH DPL

R7 Some 8-bitt Registers of the 8051

The 8051 Instruction Set

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Instruction Groups
The 8051 has 255 instructions The instructions are grouped into 5 groups

Arithmetic Logic Data Transfer Boolean Branching

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Arithmetic Instructions

ADD

8-bit addition between the accumulator (A) and a second operand.

The result is always in the accumulator. The CY flag is set/reset appropriately.

ADDC

8-bit addition between the accumulator, a second operand and the previous value of the CY flag.
Useful for 16-bit addition in two steps. The CY flag is set/reset appropriately.

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Example 16-bit Addition

Add 1E44H to 56CAH CLR MOV ADD MOV MOV ADDC MOV C A, 44H A, CAH R1, A A, 1EH A, 56H R2, A ; Clear the CY flag ; The lower 8-bits of the 1st number ; The lower 8-bits of the 2nd number ; The result 0EH will be in R1. CY = 1. ; The upper 8-bits of the 1st number ; The upper 8-bits of the 2nd number ; The result of the addition is 75H

The overall result: 750EH will be in R2:R1. CY = 0.

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Arithmetic Instructions

DA

Decimal adjust the accumulator.

Format the accumulator into a proper 2 digit packed BCD number. Operates only on the accumulator. Works only after the ADD instruction.

SUBB

Subtract with Borrow.

Subtract an operand and the previous value of the borrow (carry) flag from the accumulator.

A A - <operand> - CY. The result is always saved in the accumulator. The CY flag is set/reset appropriately.

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Example: write code that subtracts content of R6 from R7 and leave the result in R7
MOV A,R7 CLR C SUBB A, R6 MOV R7,A

Arithmetic Instructions

INC

Increment the operand by one.

The operand can be a register, a direct address, an indirect address, the data pointer.

DEC

Decrement the operand by one.

The operand can be a register, a direct address, an indirect address.

MUL AB / DIV AB
Multiply A by B and place result in A:B. Divide A by B and place result in A:B.

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Example: INC 7FH Increments the value in memory location 7FH

DEC DPL MOV R7,DPL CJNE R7, #FFH, SKIP DEC DPH SKIP: (continue)

Logical Operations

ANL / ORL

Work on byte sized operands or the CY flag.

ANL A, Rn ANL A, direct ANL A, @Ri ANL A, #data ANL direct, A ANL direct, #data ANL C, bit ANL C, /bit

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Logical Operations

XRL
Works on bytes only. XRL A, #0FFh

CPL / CLR
Complement / Clear. Work on the accumulator or a bit.

CLR P1.2

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Logical Operations

RL / RLC / RR / RRC

Rotate the accumulator.

RL and RR without the carry RLC and RRC rotate through the carry.

SWAP A

Swap the upper and lower nibbles of the accumulator. Built into conditional branching instructions.

No compare instruction.

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Data Transfer Instructions

MOV Move frm internal RAM

MOV A, Rn MOV A, direct MOV A, @Ri MOV A, #data MOV Rn, A MOV Rn, direct MOV Rn, #data MOV direct, A MOV direct, Rn MOV direct, direct MOV direct, @Ri MOV direct, #data MOV @Ri, A MOV @Ri, direct MOV @Ri, #data

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Data Transfer Operations

MOV

1-bit data transfer involving the CY flag

MOV C, bit MOV bit, C

MOV

16-bit data transfer involving the DPTR

MOV DPTR, #data

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Data Transfer Instructions

MOVC

Move Code Byte

Load the accumulator with a byte from program memory. Must use indexed addressing

MOVC MOVC

A, @A+DPTR A, @A+PC

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Data Transfer Instructions

MOVX

Data transfer between the accumulator and a byte from external data memory.
MOVX MOVX MOVX MOVX

A, @Ri A, @DPTR @Ri, A @DPTR, A

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Data Transfer Instructions

PUSH / POP
Push and Pop a data byte onto the stack. The data byte is identified by a direct address from the internal RAM locations.

PUSH POP

DPL 40H

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Data Transfer Instructions

XCH

Exchange accumulator and a byte variable

XCH A, Rn XCH A, direct XCH A, @Ri

XCHD

Exchange lower digit of accumulator with the lower digit of the memory location specified.

XCHD A, @Ri The lower 4-bits of the accumulator are exchanged with the lower 4-bits of the internal memory location identified indirectly by the index register. The upper 4-bits of each are not modified.

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Boolean Operations

This group of instructions is associated with the single-bit operations of the 8051. This group allows manipulating the individual bits of bit addressable registers and memory locations as well as the CY flag.

The P, OV, and AC flags cannot be directly altered.

This group includes:

Set, clear, and, or complement, move. Conditional jumps.

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Boolean Operations

CLR

Clear a bit or the CY flag.

CLR P1.1 CLR C

SETB

Set a bit or the CY flag.

SETB A.2 SETB C

CPL

Complement a bit or the CY flag.

CPL 40H

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; Complement bit 40 of the bit addressable memory

Boolean Operations

JC / JNC

Jump to a relative address if CY is set / cleared. Jump to a relative address if a bit is set / cleared.

JB / JNB

JB

ACC.2, <label>

JBC

Jump to a relative address if a bit is set and clear the bit.

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Branching Instructions

The 8051 provides four different types of unconditional jump instructions:

Short Jump SJMP

Uses an 8-bit signed offset relative to the 1st byte of the next instruction. Uses a 16-bit address. 3 byte instruction capable of referencing any location in the entire 64K of program memory.

Long Jump LJMP

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Branching Instructions

Absolute Jump AJMP

Uses an 11-bit address. 2 byte instruction

The upper 3-bits of the address combine with the 5-bit opcode to form the 1st byte and the lower 8-bits of the address form the 2nd byte.

The 11-bit address is substituted for the lower 11-bits of the PC to calculate the 16-bit address of the target.

The location referenced must be within the 2K Byte memory page containing the AJMP instruction.

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Indirect Jump JMP

JMP @A + DPTR

Branching Instructions

The 8051 provides 2 forms for the CALL instruction:

Absolute Call ACALL

Uses an 11-bit address similar to AJMP The subroutine must be within the same 2K page.

Long Call LCALL

Uses a 16-bit address similar to LJMP The subroutine can be anywhere.

Both forms push the 16-bit address of the next instruction on the stack and update the stack pointer.

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Branching Instructions

The 8051 provides 2 forms for the return instruction:

Return from subroutine RET

Pop the return address from the stack and continue execution there.

Return from ISV RETI

Pop the return address from the stack. Restore the interrupt logic to accept additional interrupts at the same priority level as the one just processed. Continue execution at the address retrieved from the stack.

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Branching Instructions

The 8051 supports 5 different conditional jump instructions.

ALL conditional jump instructions use an 8bit signed offset. Jump on Zero JZ / JNZ

Jump if the A == 0 / A != 0

The check is done at the time of the instruction execution.

Jump on Carry JC / JNC

Jump if the C flag is set / cleared.

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Branching Instructions

Jump on Bit JB / JNB

Jump if the specified bit is set / cleared. Any addressable bit can be specified.

Jump if the Bit is set then Clear the bit JBC

Jump if the specified bit is set. Then clear the bit.

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Branching Instructions

Compare and Jump if Not Equal CJNE

Compare the magnitude of the two operands and jump if they are not equal.
The values are considered to be unsigned. The Carry flag is set / cleared appropriately.

CJNE CJNE CJNE CJNE

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A, direct, rel A, #data, rel Rn, #data, rel @Ri, #data, rel

Branching Instructions

Decrement and Jump if Not Zero DJNZ

Decrement the first operand by 1 and jump to the location identified by the second operand if the resulting value is not zero.
DJNZ DJNZ

Rn, rel direct, rel

No Operation

NOP

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SETB bit CLR bit

SETB SETB SETB SETB SETB
Note:

; bit=1 ; bit=0
; CY=1 ;bit 0 from port 0 =1 ;bit 7 from port 3 =1 ;bit 2 from ACCUMULATOR =1 ;set high D5 of RAM loc. 20h

C P0.0 P3.7 ACC.2 05

CLR instruction is as same as SETB i.e.: CLR C ;CY=0 But following instruction is only for CLR: CLR A ;A=0

LOOP and JUMP Instructions

Conditional Jumps :
JZ
JNZ DJNZ

Jump if A=0
Jump if A/=0 Decrement and jump if A/=0

CJNE A,byte
CJNE reg,#data JC JNC JB JNB JBC

Jump if A/=byte
Jump if byte/=#data Jump if CY=1 Jump if CY=0 Jump if bit=1 Jump if bit=0 Jump if bit=1 and clear bit