CS 61C: Great Ideas in Computer Architecture: Course Introduction
CS 61C: Great Ideas in Computer Architecture: Course Introduction
Research: Synthetic Biology Teaching: EE128, EE40, CS61C (Su11, Su12, Sp13) Interests:
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Agenda
Course Overview
Six Great Ideas in Computer Architecture
Machine Structures
Application (ex: browser) Compiler Operating System (Mac OSX) I/O system
CS 61C
Instruction Set Architecture
Software Hardware
Assembler Processor
Memory
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New-School: Parallelism
Software Parallel Requests
Assigned to computer e.g. search Garcia Assigned to core e.g. lookup, ads
Hardware
Warehouse Scale Computer Smart Phone
Leverage
Parallel Instructions
> 1 instruction @ one time e.g. 5 pipelined instructions
Core
Parallel Data
> 1 data item @ one time e.g. add of 4 pairs of words
Hardware descriptions
All gates functioning in parallel at same time
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Cache Memory
Logic Gates
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Enabling Tech: Wireless networking, smartphones Big Players: Apple, Nokia, Cost: $500, Target: Consumers on the go Using: Objective C, Android OS
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iPhone Innards
I/O
Processor
I/O
Memory You will learn about multiple processors, the memory hierarchy, and I/O in 61C
I/O
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Enabling Tech: Local Area Networks, broadband Internet Big Players: Amazon, Google, Target: Transient users or users who cannot afford highend equipment
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Enabling Tech: Local Area Networks, cheap servers Cost: $200M clusters + maintenance costs Target: Internet services and PMDs Usages: MapReduce, Ruby on Rails
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e.g. words, colors, data, logic, Hardware Architecture Description (e.g. block diagrams) code, even other numbers
Architecture Implementation Logic Circuit Description (Circuit Schematic Diagrams)
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2,000 Years
Jim Gray Turing Award B.S. Cal 1966 2 Years Ph.D. Cal 1969!
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6 Disk
100
Memory
Sacramento
This Campus This Room My Head
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1+1=2
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1+1=2
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1+1=1
FAIL!
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Agenda
Course Overview
Six Great Ideas in Computer Architecture
Course Information
This information can also be found on the course syllabus Website: http://inst.eecs.berkeley.edu/~cs61c/su13 Instructor: Justin Hsia Teaching Assistants: Albert Magyar, Jeffrey Dong, Justin Fu, Kevin Yeun, Sagar Karandikar, Shaun Benjamin Textbooks: average 15 pages of reading/week
Patterson & Hennessey, Computer Organization and Design, Revised 4th Edition (not 3rd Edition, not Asian 4th Edition) Kernighan & Ritchie, The C Programming Language, 2nd Edition Barroso & Holzle, The Datacenter as a Computer, 1st Edition (free!)
Midterm (24%): Friday, July 19 @ 9am Final (26%): Friday, August 16 @ 9am Participation and Altruism (5%)
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Projects
Software Parallel Requests
Assigned to computer e.g. search Garcia Assigned to core e.g. lookup, ads
Hardware
Warehouse Scale Computer
Leverage
Parallel Instructions
>1 instruction @ one time e.g. 5 pipelined instructions
Core
Parallel Data
> 1 data item @ one time e.g. add of 4 pairs of words
Hardware descriptions
All gates functioning in parallel at same time
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Altruism
Helping others in lab, discussion, and on Piazza
Peer Instruction
Increase real-time learning in lecture, test understanding of concepts vs. details
mazur-www.harvard.edu/education/pi.phtml
components that almost never fail (B) Memory hierarchy goal is to look as fast as most expensive memory, as big as cheapest (C) Moores Law means computers will continue to get put twice as many transistors/chip every 2 years without fail
(D)
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Pedagogic Comments
Deep learning does not happen in lecture
Learn by doing: labs, discussions, and assignments
Engaging the material outside of class and lab is critical to your success
Study groups, testing out your own questions Talking with others helps solidify your own understanding
Architecture of a Lecture
Full
Attention
Summary + Bonus
20 25
50 53
78 80
Time (minutes)
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Last Things
Discussions, labs, and OHs start immediately
Yes, that means today! Switching sections: if you find another 61C student willing to swap lab, talk to your TAs Attend whichever discussion you want, as long as there is enough physical room
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Agenda
Course Overview
Six Great Ideas in Computer Architecture
Number Representation
Numbers are an abstract concept!
Recognize that these are arbitrary symbols
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Number Bases
Key terminology: digit (d) and base (B) Value of i-th digit is dBi where i starts at 0 and increases from right to left
n digit number dn-1dn-2 ... d1d0 value = dn-1Bn-1 + dn-2Bn-2 + ... + d1B1 + d0B0
In base B, each digit is one of B possible symbols Base is indicated using either a prefix or a subscript
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Binary (base 2)
Symbols: 0, 1 Notation: 101011two = 0b101011
For convenience, can group into nibbles (4 bits) and bytes (8 bits)
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Keep in mind that the same bit pattern will mean different things depending on how you choose to interpret it
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Alt text: The Wikipedia page "List of Numbers" opens with "This list is incomplete; you can help by expanding it. (Source: http://xkcd.com/899)
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Unsigned Integers
Represent only non-negative (unsigned) integers:
0000two = 0ten 0001two = 1ten ... 0110two = 6ten 0111two = 7ten 1000two = 8ten 1001two = 9ten ... 1110two = 14ten 1111two = 15ten
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Signed Integers
n bits can represent 2n different things
Ideally, want the range evenly split between positive and negative
How do we want to encode zero? Can we encode them in such a way that we can use the same hardware regardless of whether the numbers are signed or unsigned?
e.g. incrementing pos/neg numbers
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0000two = +0ten 0001two = +1ten ... 0110two = +6ten 0111two = +7ten 1000two = -0ten 1001two = -1ten ... 1110two = -6ten 1111two = -7ten
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Biased Notation
Like unsigned, but shifted so zero is in the middle:
0000two = -7ten 0001two = -6ten ... 0110two = -1ten 0111two = 0ten 1000two = +1ten 1001two = +2ten ... 1110two = +7ten 1111two = +8ten
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Ones Complement
New negation procedure complement the bits:
0000two = +0ten 0001two = +1ten ... 0110two = +6ten 0111two = +7ten 1000two = -7ten 1001two = -6ten ... 1110two = -1ten 1111two = -0ten
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Twos Complement
Like Ones Complement, but shift negative #s by 1:
0000two = 0ten 0001two = +1ten ... 0110two = +6ten 0111two = +7ten 1000two = -8ten 1001two = -7ten ... 1110two = -2ten 1111two = -1ten
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Can still use MSB as sign bit To negate: Flip the bits and add one
Example: +7 = 0b 0000 0111, -7 = 0b 1111 1001
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Overflow
Overflow is when the result of an arithmetic operation cant be represented by the hardware bits
i.e. the result is mathematically incorrect
Examples:
Unsigned: Twos: 0b11 + 110 = 0b00 = 0? 0b011 + 110 = 0b100 = -2(n-1)ten?
0b 0000
0001
0010 unsigned
1110
1111
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Sign Extension
Want to represent the same number using more bits than before
Easy for positive #s (add leading 0s), more complicated for negative #s Sign and magnitude: add 0s after the sign bit Ones complement: copy MSB Twos complement: copy MSB
Example:
Sign and magnitude: 0b 11 = 0b 1001 Ones/Twos complement: 0b 11 = 0b 1111
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Summary (1/2)
CS61C: Learn 6 Great Ideas in Computer Architecture to enable high performance programming via parallelism
1. 2. 3. 4. 5. 6.
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Layers of Representation/Interpretation Technology Trends Principle of Locality/Memory Hierarchy Parallelism Performance Measurement and Improvement Dependability via Redundancy
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Summary (2/2)
Number Representation: How to represent positive and negative integers using binary
Unsigned: Interpret numeral in base 2 Signed: Twos Complement Biased: Subtract bias Sign extension must preserve signed number
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