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Programmable ASIC Design: Haibo Wang ECE Department Southern Illinois University Carbondale, IL 62901

Asic introduction

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Huzur Ahmed
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92 views

Programmable ASIC Design: Haibo Wang ECE Department Southern Illinois University Carbondale, IL 62901

Asic introduction

Uploaded by

Huzur Ahmed
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
You are on page 1/ 25

ECE428 :

Programmable ASIC Design

Haibo Wang ECE Department Southern Illinois University Carbondale, IL 62901


1-1

The evolution of Integrated Circuits


1948: Invention of transistor (Bell Labs)

1958: Invention of Integrated Circuits


The idea of making a whole circuit-transistors, wires, and everything else-was invented by Jack Kilby at Texas Instruments and Robert Noyce at Fairchild Semiconductor almost at the same time.

1965: Moores Law


In 1965, Gordon Moore at Intel made a prediction that semiconductor technology will double its effectiveness every 18 months

1-2

Moores Law in Microprocessors


1000 Transistors (MT) 100 10 1 486 386 286 8085 8086 8080 8008 4004 1980 1990 Year 2000 2010

2X growth in 1.96 years!


P6 Pentium proc

0.1
0.01

0.001 1970

Source from http://infopad.eecs.berkeley.edu/~icdesign


1-3

Clock frequencies of Microprocessors


10000 Frequency (Mhz) 1000 100 486 10 1 0.1 1970 8085

Doubles every 2 years


P6 Pentium proc

8086 286

386

8080 8008 4004 1980 1990 Year 2000 2010

Source from http://infopad.eecs.berkeley.edu/~icdesign


1-4

Classifications of Integrated Circuits


Microprocessors

Memory chips (SRAM, DRAM, Flash, ROM, PROM)


Standard Components (74LS..) Application-Specific Integrated Circuits
Widely used in communication, network, and multimedia systems For a given application, ASIC solutions are normally more effective than the solutions based on running software on microprocessors Many chips in cellular phones, network routers, and game consoles are ASICs Most SoC (Systems-on-a-Chip) chips are ASICs
1-5

ASIC Design Methodologies


ASIC Design Methodology

Full-custom design
This approach is extremely slow, expensive It is only used to design very high performance systems

Standard-cell based design


This approach is reasonable fast, less expensive Most ASICs are currently designed using this method

Gate-array based design


This approach is fast and less expensive ASIC performance are relatively slow

FPGA based design


The design process is very fast and cost effective ASIC performance are slow

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Full-Custom Design Methodology


Function Partition

Layout Design Including placement & routing


Schematic Design Including transistor sizing Fail Function And Timing verification Pass ASIC Chips It is a time consuming manual process, not pre-developed libraries needed.
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Post-Layout simulation Pass Go to fabrication

Fail

Full-Custom Design Methodology


Design a chip from scratch. Engineers design some or all of the logic cells, circuits, and the chip layout specifically for a full-custom IC. Custom mask layers are created in order to fabricate a full-custom IC. Advantages: complete flexibility, high degree of optimization in performance and area. Disadvantages: large amount of design effort, expensive.

1-8

Standard-Cell Based Design Methodology


High-level (RTL or behavioral-level) design Fail VHDL or Verilog coding

High-level verification
Pass Logic synthesis

VHDL or Verilog simulation

Logic gate library

Fail

Gate-level verification Pass

Placement & Routing


Fail Pass

Cell layout library

Post-Layout verification

Go to fabrication
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It is highly automated, but need pre-developed libraries.

Standard-Cell Based Design Methodology


Use pre-developed logic cells from standard-cell library as building blocks. As full-custom design, all mask layers need to be customized to fabricate a new chip. Advantages: save design time and money, reduce risk compared to full-custom design.

Disadvantages: still incurs high non-recurring-engineering (NRE) cost and long manufacture time.
Library Cells

D
B Chip layout

A
D

A
C

A
C

B
D

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Gate-Array Based Design Methodology


Generating schematic (netlist) The netlist can be designed using full-custom or standard-cell based design method

Placement & Routing

Cell layout library

Post-Layout verification

Make the final connections for the pre-fabricated gate array base

Pre-fabricated gate array template It contains transistors without connections

ASIC Chips
1-11

This approach is faster than the standard-cell based approach because part of the fabrication process has been complete.

Gate-Array Based Design Methodology


Parts of the chip (transistors) are pre-fabricated, and other parts (wires) are custom fabricated for a particular customers circuit.

Gate Array

Sea-of-Gates

Advantages: cost saving (fabrication cost of a large number of identical template wafers is amortized over different customers), shorter manufacture lead time. Disadvantages: performance not as good as full-custom or standard-cell-based ICs.
1-12

FPGA Based Design Methodology


Schematic Capture netlist FPGA cell library Fail Verification Pass Generate FPGA Bit Stream FPGA This approach has extremely fast turn-out time since FPGA devices has been fabricated.
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HDL coding & Logic Synthesis

Implementation

Technology mapping Placement & routing Timing verification Download

Comparison of Design Methodologies


Full-custom design Speed Integration density High-volume device cost low-volume device cost Custom mask layer Fabrication time Time to Market Risk reduction Future design modification +++ +++ ++ --All --------Standard-cell based design ++ ++ ++ -All ----Gate-array based design + + + + Some ++ FPGA-based design -+ +++ None +++ +++ +++ +++
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+ desirable; - not desirable

Why do we want FPGAs


Advantages of using FPGAs
Fast turn-out time The ability of re-programming
The capability of dynamic reconfiguration

FPGA Applications
Ideal platform for prototyping Providing fast implementation to reduce time-to-market Cost effective solutions for products with small volumes on demand Implementing hardware systems requiring re-programming flexibility Implementing dynamically re-configurable systems
1-15

FPGA Market
Market Share in 1998

Total Revenue is above two billion U.S. Dollar Source from http://www.optimagic.com/

Current FPGA revenue is about 3.6B USD. Major players include: Xilinx, Altera, Actel, Lattice, Atmel, Cypress, QuickLogic, SiliconBlue

1-16

The State-of-Art of FPGAs


Various types of FPGAs are available for different applications Modern FPGAs are fabricated using the most advanced technology
and are capable to implement very high performance systems
For example, the latest Xilinx Virtex-II Pro FPGAs are fabricated using 90 nm technology, containing more than one million gates. Such devices also include PowerPC microprocessor, on-chip memories, and 3.125Gbit/s I/O interfaces.

Currently, FPGAs are widely used in implementing communication


systems, configurable computers, and DSP applications
1-17

Typical FPGA Architectures


FPGA I/O cell

Configurable Logic Block

Configurable Interconnects

FPGA I/O cell

Configurable Interconnects
1-18

Examples of FPGA Architectures

http://www.xilinx.com

1-19

Examples of FPGA Architectures

www.latticesemi.com/images/img24483.gif

1-20

Examples of FPGA Architectures

http://www.xilinx.com

1-21

Examples of FPGA Package


Back view of Ball Grid Array (BGA)

An FPGA with BGA package on PCB

www.altera.com

http://www.bluemelon.org/index.php/Projects/FPGA_design

1-22

Examples of FPGA Applications


Reconfigurable computing & hardware accelerator

http://www.fastertechnology.com/

1-23

Examples of FPGA Applications


40Gbps datapath for internet connection

http://www.xilinx.com/publications/prod_mktg/pn2094.pdf

1-24

Examples of FPGA Applications


Logic emulation

www.applistar.com/top/DN9000K10.jpg
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