Introduction to

Analog-Digital-Converter
Dr.-Ing. Frank Sill
Department of Electrical Engineering, Federal University of Minas Gerais,
Av. Antnio Carlos 6627, CEP: 31270-010, Belo Horizonte (MG), Brazil

[email protected]
http://www.cpdee.ufmg.br/~frank/
Copyright Sill, 2008 Analog Digital Converter 2
Agenda
Introduction
Characteristic Values of ADCs
Nyquist-Rate ADCs
Oversampling ADC
Practical Issues
Low Power ADC Design
Copyright Sill, 2008 Analog Digital Converter 3
Introduction
ADC = Analog-Digital-Converter
Conversion of audio signals (mobile micro,
digital music records, ...)
Conversion of video signals (cameras,
frame grabber, ...)
Measured value acquisition (temperature,
pressure, luminance, ...)
Copyright Sill, 2008 Analog Digital Converter 4
ADC - Scheme
Sample
& Hold
Quantization
f
sample
Analog
Digital
Analog input can be voltage or current (in the following
only voltage)
Analog input can be positive or negative (in the following
only positive)
Copyright Sill, 2008 Analog Digital Converter 5
2. Characteristic Values of ADCs
Which values characterize an ADC?
What kind of errors exist?
What is aliasing?
Copyright Sill, 2008 Analog Digital Converter 6
ADC Values
Resolution N: number of discrete values to represent
the analog values (in Bit)
8 Bit = 2
8
= 256 quantization level,
10 Bit = 2
10
= 1024 quantization level
Reference voltage V
ref
: Analog input signal V
in
is
related to digital output signal D
out
through V
ref
with:

V
in
= V
ref
(D
0
2
-1
+ D
1
2
-2
+ + D
N-1
2
-N
)

Example: N = 3 Bit, V
ref
= 1V, D
out
= 011
=> V
in
= 1V ( 2
-2
+ 2
-3
) = 1V (0.25 + 0.125) = 0.375V
ADC
V
in
D
out
= D
0
D
1
D
N-1
V
ref
Copyright Sill, 2008 Analog Digital Converter 7
ADC Values contd
V
LSB
: Minimum measurable voltage difference in
ideal case (LSB least significant Bit)
V
LSB
= V
ref
/ 2
N

V
in
= V
LSB
(D
0
2
N-1
+ D
1
2
N-2
+ + D
N-1
2
0
)
Example: N = 3 Bit, V
ref
= 1V, D
out
= 011
=> V
LSB
= 1V / 2
3
= 0.125V
=> V
in
= 0.125V ( 2
1
+ 2
0
) = 0.125V 3 = 0.375V
V: Voltage difference between two logic level
Ideal: all V = V
LSB
V
FSR
: Difference between highest and lowest
measurable voltages (FSR full scale range)
Copyright Sill, 2008 Analog Digital Converter 8
ADC Values contd
SNR: Signal to Noise Ratio
Ratio of signal power to noise power



ENOB: Effective Number of Bits
Effective resolution of ADC under observance of all noise and
distortions




SINAD (SIgnal to Noise And Distortion) ratio of fundamental
signal to the sum of all distortion and noise (DC term removed)
Comparison of SINAD of ideal and real ADC with same word
length
02 . 6
76 . 1
=
SINAD
ENOB
, 10log
signal signal
db
noise noise
P P
SNR SNR
P P
| |
= =
|
\ .
Copyright Sill, 2008 Analog Digital Converter 9
Ideal ADC
000
001
010
011
100
101
110
111
8
ref
V
D
i
g
i
t
a
l

O
u
t
p
u
t

D
o
u
t
Analog Input V
in
7
8
ref
V
4
8
ref
V
V, V
LSB
V
FSR
Copyright Sill, 2008 Analog Digital Converter 10
Further ADC Values
Bandwidth: Maximum measurable frequency of the
input signal
Power dissipation
Conversion Time: Time for conversion of an analog
value into a digital value (interesting in pipeline and
parallel structures)
Sampling rate (f
samp
): Rate at which new digital values
are sampled from the analog signal (also: sample
Errors: Quantization, offset, gain, INL, DNL, missing
codes, non-monotonicity
Copyright Sill, 2008 Analog Digital Converter 11
Quantization Error
000
001
010
011
100
101
110
111
in
V
2
LSB
V
2
LSB
V

7
8
ref
V
D
o
u
t
c
2 2
LSB LSB
V V
c s <
Copyright Sill, 2008 Analog Digital Converter 12
Quantization Error (3-Bit Flash)
Eugenio Di Gioia, Sigma-Delta-A/D-Wandler, 2007
sample
sample
A
m
p
l
i
t
u
d
e

E
r
r
o
r

Copyright Sill, 2008 Analog Digital Converter 13
Offset Error
Parallel shift of the whole curve
E.g. caused by difference in ground line voltages
offset
000
001
010
011
100
101
110
111
8
ref
V
4
8
ref
V
7
8
ref
V
D
o
u
t
in
V
Copyright Sill, 2008 Analog Digital Converter 14
Gain Error
Corresponds to too small or to large but equal V
E.g. caused by too small or too large V
ref
gain
000
001
010
011
100
101
110
111
8
ref
V 4
8
ref
V
7
8
ref
V
D
o
u
t
in
V
Copyright Sill, 2008 Analog Digital Converter 15
Differential Non-Linearity (DNL)
Deviation of V from V
LSB
value (in V
LSB
)
Defined after removing of gain
E.g. Caused by mismatch of the reference elements
000
001
010
011
100
101
110
111
8
ref
V 4
8
ref
V
7
8
ref
V
D
o
u
t
in
V
1
2
LSB
DNL V =
1
2
LSB
DNL V =
V
LSB
V
LSB
1 1

2 2
LSB LSB
DNL V V V = A =
1
1.5
2
LSB LSB
DNL V V V = A =
Copyright Sill, 2008 Analog Digital Converter 16
Integral Non-Linearity (INL)
Deviation from the straight line (best-fit or end-point) (in V
LSB
)
Defined after removing of gain and offset
E.g. caused by mismatch of the reference elements
000
001
010
011
100
101
110
111
8
ref
V 4
8
ref
V
7
8
ref
V
D
o
u
t
in
V
1
2
LSB
INL V =
1
4
LSB
INL V =
Copyright Sill, 2008 Analog Digital Converter 17
Missing Codes
Some bit combinations never appear
Occurs, if maximum DNL > 1 V
LSB
or maximum INL > 0.5 V
LSB
000
001
010
011
100
101
110
111
8
ref
V
4
8
ref
V
7
8
ref
V
D
o
u
t
in
V
Missing Code
Copyright Sill, 2008 Analog Digital Converter 18
Non-Monotonicity
Lower conversion result for a higher input voltage
Includes that same conversion may result from two
separate voltage ranges
000
001
010
011
100
101
110
111
8
ref
V
4
8
ref
V
7
8
ref
V
D
o
u
t
in
V
Non-Monotonicity
Ideal
curve
Copyright Sill, 2008 Analog Digital Converter 19
Aliasing
Too small sampling rate f
samp
(under-sampling) can lead
to aliasing ( = frequency of reconstructed signal is to low)
Nyquist criterion:
f
samp
more than two times higher than highest
frequency component f
in
of input signal: f
samp
> 2f
in
Input signal
(with f
in
)
Reconstructed
output signal
Measured data points
(sample rate: f
samp
)
Copyright Sill, 2008 Analog Digital Converter 20
3. Nyquist-Rate ADCs
How can Nyquist-rate ADCs be grouped?
What is a dual slope ADC?
What is a successive approximation ADC?
What is an algorithmic ADC?
What is a flash ADC?
What is a pipelined ADC?
What are the pros and cons of the
Nyquist-rate ADCs?

Copyright Sill, 2008 Analog Digital Converter 21
Nyquist-Rate ADCs
Sampling frequency f
samp
is in the same range as
frequency f
in
of input signal
Low-to-medium speed and high accuracy ADCs
Integrating
Medium speed and medium accuracy ADCs
Successive Approximation
Algorithmic
High speed and low-to-medium accuracy ADCs
Flash
Two-Level Flash
Pipelined
Copyright Sill, 2008 Analog Digital Converter 22
Integrating (Dual Slope) ADCs
Phase 1: Integration (capacitor C1) of V
in
in known time T
load

Q
load
= V
in
/ R1 T
load

Phase 2: Integration of reference voltage -V
ref
until V
out
= 0
and estimation of time T
Q
ref
= -V
ref
/ R1 T = -Q
load
=> V
in
= V
ref
T / T
load
Independent of R1 und C1!

V
in
-V
ref
S1
S2
C1
Control
logic
Counter
Comparator
D
0
D
1
D
2
D
3
D
N-1
Integrator
V
out
R1
Copyright Sill, 2008 Analog Digital Converter 23
Integrating (Dual Slope) ADCs contd
V
o
l
t
a
g
e
Time
V
in3
V
in2
V
in1
Phase 1 Phase 2
T
1
T
2
T
3
T
load
constant
slope
slope depends
on V
in
Copyright Sill, 2008 Analog Digital Converter 24
Integrating ADCs: pros and cons
Simple structure (comparator and
integrator are the only analog
components)
Low Area / Low Power

Slow
Time intervals are not constant
Copyright Sill, 2008 Analog Digital Converter 25
Successive Approximation ADC
Generate internal analog signal V
D/A
Compare V
D/A
with input signal V
in
Modify V
D/A
by D
0
D
1
D
2
D
N-1
until closest possible
value to V
in
is reached

S&H
Logic
DAC
D
0
D
1
D
N-1
V
in
V
ref
V
D/A
Copyright Sill, 2008 Analog Digital Converter 26
Successive Approximation ADC contd
S&H
Logic
DAC
D
0
D
1
D
N-1
V
in
V
ref
V
D/A
Comparsion of V
D/A
with
2
V
ref
2
in
V
ref
V >
2
in
V
ref
V <
Comp. w.
4
V
ref
Comp. w.
3
4
V
ref
4
in
V
ref
V >
4
in
V
ref
V <
4
in
V
ref
V >
4
in
V
ref
V <
Copyright Sill, 2008 Analog Digital Converter 27
Successive Approximation ADC contd
P. Fischer, VLSI-Design - ADC und DAC, Uni Mannheim, 2005
Iterations
in
V
8
ref
V
4
8
ref
V
7
8
ref
V
1. 2. final
result
V
D/A
100
110
010
111
101
011
001
111
110
101
100
011
010
001
000
3.
Copyright Sill, 2008 Analog Digital Converter 28
Successive Approx.: pros and cons
Low Area / Low Power

High effort for DAC
Early wrong decision leads to false result
Copyright Sill, 2008 Analog Digital Converter 29
Algorithmic ADC
Same idea as successive approximation ADC
Instead of modifying V
ref
doubling of error
voltage (V
ref
stays constant)

V
in S&H
S&H
X2
S1
V
ref
/4
-V
ref
/4
S2
D
0
D
1
D
N-1
Shift register
Copyright Sill, 2008 Analog Digital Converter 30
Algorithmic ADC cont
Start
Sample V = V
in
, i = 1
D
i
= 1
V > 0
D
i
= 0
V = 2(V - V
ref
/4) V = 2(V + V
ref
/4)
i = i+1
i > N
Stop
yes
no
yes
V
in
S&H
X2
S1
V
ref
/4
-V
ref
/4
S2
D
0
D
1
D
N-1
Shift register
no
S&H
D.A.. Johns, K. Martin, Analog Integrated Circuit design, John Wiley & Sons, 1997
Copyright Sill, 2008 Analog Digital Converter 31
Algorithmic ADC: pros and cons
Less analog circuitry than Succ. Approx.
ADC
Low Power / Low Area

High effort for multiply-by-two gain amp


Copyright Sill, 2008 Analog Digital Converter 32
Flash ADC
V
in
V
ref
Over range
D
0
D
1
D
N-1
(2
N
-1) to N
encoder
R/2
R
R/2
R
R
R
R
R
R
V
in
connected with 2
N

comparators in parallel
Comparators connected
to resistor string
Thermometer code
R/2-resistors on bottom
and top for 0.5 LSB
offset


Copyright Sill, 2008 Analog Digital Converter 33
Some Flash ADC design issues
Input capacitive loading on V
in
Switching noise if comparators switch at the
same time
Resistors-string bowing by input currents of
bipolar comparators (if used)
Bubble errors in the thermometer code based on
comparators metastability

Copyright Sill, 2008 Analog Digital Converter 34
Flash ADC: pros and cons
Very fast

High effort for the 2
N
comparators
High Area / High Power

Recommended for 6-8 Bit and less

Copyright Sill, 2008 Analog Digital Converter 35
Two-Level Flash ADC
Conversion in two steps:
1. Determination of MSB-Bits and reconverting of
digital signal by DAC
2. Subtraction from V
in
and determination of LSB-Bits
F.e. 8-Bit-ADC: Flash: 2
8
=256 comparators, Two-level:
22
4
= 32 comparators



N/2-Bit
Flash ADC
x2
N
MSB (D
0
D
N/2-1
) LSB (D
N/2
D
N-1
)
N/2-Bit
Flash ADC
gain amp
V
in
N/2-Bit
DAC
Copyright Sill, 2008 Analog Digital Converter 36
Two-Level Flash ADC: pros and cons
Same throughput as Flash ADC
Less area, less power, less capacity loading
than Flash ADC
Easy error-correction after first stage

Larger latency delay than Flash ADC
Design of N/2-Bit-DAC

Currently most popular approach for high-
speed/medium accuracy ADCs

Copyright Sill, 2008 Analog Digital Converter 37
Pipelined ADCs
Extension of two-level architecture to multiple stages
(up-to 1 Bit per stage)
Each stage is connected with CLK-signal
Pipelined conversion of subsequent input signals
First result after m CLK cycles (m - amount of
stages)
Stages can be different
Stage 1 Stage 2 Stage m
V
in,0
V
in,1
V
in,m-1
CLK
D
0
D
k-1
D
k
D
2k-1 D
mk
D
N-1
Copyright Sill, 2008 Analog Digital Converter 38
Pipelined ADCs: Scheme
k-Bit
ADC
k-Bit
DAC
x2
k
k Bits
V
in,i
Stage 1
S&H
Stage 2 Stage m
V
in,0
V
in,i+1
V
in,1
V
in,m-1
Time Alignment & Digital Error Correction
D
0
D
1
D
N-1
CLK
CLK
Copyright Sill, 2008 Analog Digital Converter 39
Pipelined ADC: pros and cons
High throughput
Easy upgrade to higher resolutions

High demands on speed and accuracy on gain
amplifier
High CLK-frequency needed
High Power

Copyright Sill, 2008 Analog Digital Converter 40
4. Oversampling ADCs
What are the problems of the quantization
noise?
How does oversampling work?
What is noise shaping?
What is a sigma-delta ADC?


Copyright Sill, 2008 Analog Digital Converter 41
Quantization Error (recap)
000
001
010
011
100
101
110
111
in
V
2
LSB
V
2
LSB
V

7
8
ref
V
D
o
u
t
c
2 2
LSB LSB
V V
c s <
Copyright Sill, 2008 Analog Digital Converter 42
Quantization Noise
Quantization error with probability density p() can be
approximated as uniform distribution







( )
/ 2
/ 2
1
1

LSB
LSB
V
V
LSB
p d
p
V
c c

=
=
}
p()
2
LSB
V

2
LSB
V

p
Copyright Sill, 2008 Analog Digital Converter 43
Quantization Noise contd
Quantization noise reduces Signal-Noise-Ration (SNR)
of ADC
Estimation of SNR with Root Mean Square (RMS) of
input signal (V
in_RMS
) and of noise signal (V
qn_RMS
)
SNR = V
in_RMS
/ V
qn_rms

Every additional Bit halves V
LSB
V
qn_RMS
decreases by
6 dB with every new Bit
F.e. V
in
is sinusoidal wave SNR = (6.02 N + 1.76) dB


( )
1/ 2
1/ 2
/ 2
2 2
_
/ 2
1
12
LSB
LSB
V
LSB
qn RMS
LSB
V
V
V p d d
V
c c c c c
+

(
(
= = =
(
(
(

} }
Copyright Sill, 2008 Analog Digital Converter 44
Quantization Noise contd
Quantization noise can be approximated as white noise
Spectral density S

(f) of quantization noise is constant

(f)
2
s
f

2
s
f
f
1
12
LSB
s
V
S
f
=
( )
/ 2
2
2
/ 2
12
s
s
f
LSB
f
V
P S f df
c c
+

= =
}
Copyright Sill, 2008 Analog Digital Converter 45
Quantization Error (3-Bit Flash, recap)
Eugenio Di Gioia, Sigma-Delta-A/D-Wandler, 2007
sample
sample
A
m
p
l
i
t
u
d
e

E
r
r
o
r

Copyright Sill, 2008 Analog Digital Converter 46
Oversampling (OS)
Quantized signal is low-pass filtered to frequency f
0

elimination of quantization noise greater than f
0








Oversampling rate (OSR) is ratio of sampling frequency f
s

to Nyquist rate of f
0





2
s
f

2
s
f
f
H(f)
|H(f)|
0
2
f
0
2
f

1
V
in
(f)
0
2
s
f
OSR
f
=
Copyright Sill, 2008 Analog Digital Converter 47
OS in Frequency Domain
P
o
w
e
r
f
s
/2 = OSRf
0
/2
f
0
/2 f
Digital filter response
Oversampling
P
o
w
e
r
f
0
/2 f
Signal
amplitude
Average
quantization noise
Copyright Sill, 2008 Analog Digital Converter 48
Oversampling contd
Quantization noise power P

results to:




Doubling of f
s
increases SNR by 3 dB
Equivalently to a increase of resolution by 0.5 Bits

F.e. V
in
is sinusoidal wave
SNR = (6.02 N + 1.76 + 10log [OSR]) dB

0
0
/ 2 / 2
2
2
2 2
/ 2 / 2
1
( ) ( )
12
s
s
f f
LS
f
B
f
V
P S f H f df S df
OSR
c c
+ +

| |
= = =
|
\ .
} }
Copyright Sill, 2008 Analog Digital Converter 49
OS signal reconstruction
Signal results from relation of 0s and 1s
n
Nyquist -ADC
Oversampling - ADC
1V
0.66 V
0.33 V
Nyquist - ADC
Oversampling
00000011111111110000000
0.33
0.33
x[n]
2 2
_
0.33 0.33
2
RMS Nyquist
V
+
=
( ) ( )
2 2 2 2
_
5 1 7 0 5 1 7 0
24
RMS Oversampling
V
+ + +
=
Copyright Sill, 2008 Analog Digital Converter 50
Noise Shaping (NS)
Next trick: feedback loop
Quantization noise signal is negative coupled with input






Based on high gain of closed-loop at low frequencies:
Quantization noise reduced at low frequencies
Quantization noise is shaped = moved to higher frequencies



H(z)
Integrator Quantizer
DAC
X Y
E
( )
1
1
1 1
H
Y X E X H
H H
= + ~ >>
+ +
Copyright Sill, 2008 Analog Digital Converter 51
Noise Shaping contd
Oversampling and noise shaping:
Doubling of f
s
increases SNR by 9 dB
Equivalently to a increase of resolution by 1.5 Bits
F.e. V
in
is sinusoidal wave
SNR = (6.02 N + 1.76 5.17 + 30log [OSR]) dB

up to f
in
= 100 kHz (and more)
1-Bit Quantizer (Comperator)
1-Bit DAC
Copyright Sill, 2008 Analog Digital Converter 52
OS and NS in Frequency Domain
P
o
w
e
r
f
s
/2 = OSRf
0
/2
f
0
/2 f
Digital filter response
Oversampling
P
o
w
e
r
f
s
/2 f
0
/2 f
Oversampling and noise shaping
P
o
w
e
r
f
0
/2 f
Signal
amplitude
Average
quantization noise
Copyright Sill, 2008 Analog Digital Converter 53
DAC
Comparator
V
ref
= 2.5 V
V
in
= 1.2 V
( ) ( )
in
v t t dt c = E
}
( ) ( )
in
v t t c = A
Sigma Delta ADC Example
1.2
-1.3
3.7
-1.3
1.2
-0.1
3.6
2.3
1
0
1
1
2.5
-2.5
2.5
2.5
Copyright Sill, 2008 Analog Digital Converter 54
Sigma Delta ADC Example (Curves)
http://www.beis.de/Elektronik/DeltaSigma/DeltaSigma_D.html
H(z)
I
n
t
e
g
r
a
t
o
r
1
B
i
t

-
Q
u
a
n
t
i
z
e
r
CLK
D
A
C
Copyright Sill, 2008 Analog Digital Converter 55
Sigma Delta ADC: pros and cons
High resolution
Less effort for analog circuitry

Low speed
High CLK-frequency

Currently popular for audio applications


Copyright Sill, 2008 Analog Digital Converter 56
5. Practical issues
What are the performance limitations of
ADCs?
What are the differences between PCB-
and IC-designs?
Are there hints to improve the ADC
design?
What are S&H circuits?
Copyright Sill, 2008 Analog Digital Converter 57
Performance Limitations
Analog circuit performance limited by:
High-frequency behavior of applied components
Noise
Crosstalk (analog analog, analog digital)
Power supply coupling
Thermal noise (white noise)
Parasitic components (capacitances, inductivities)
Wire delays
Copyright Sill, 2008 Analog Digital Converter 58
Parasitic Component Example
Effect of 1pF capacitance on inverting input of
an opamp:

Mancini, Opamps for everyone, Texas Instr., 2002
Copyright Sill, 2008 Analog Digital Converter 59
Noise Demands Examples
Example 1: V
ref
= 5V, 10 Bit resolution
V
LSB
= 5V / 2
10
= 5V / 1024 = 4.9 mV
Every noise must be lower than 4.9 mV

Example 2: V
ref
= 5V, 16 Bit resolution
V
LSB
= 5V / 2
16
= 5V / 65536 = 76 V
Every noise must be lower than 76 V
Copyright Sill, 2008 Analog Digital Converter 60
PCB- versus IC-Design
PCB: Printed Circuit Board, IC: Integrated Circuit
Noise in PCB-circuits much higher than in ICs
Influences of parasitics in PCB-circuits much
higher than in ICs
High-frequency behavior of PCB-circuits much
worse than of ICs
Wire delays in PCB much higher than in ICs

High accuracy, high speed, high
bandwidth ADCs only possible in ICs!


Copyright Sill, 2008 Analog Digital Converter 61
For PCB and IC:
Keep ground lines separate!
Dont overlap digital and analog signal wires!





Dont overlap digital and analog supply wires!
Locate analog circuitry as close as possible to the I/O
connections!
Choose right passive components for high-frequency
designs! (only PCB)
Some Hints for Mixed Signal Designs


Mancini, Opamps for everyone, Texas Instr., 2002
Copyright Sill, 2008 Analog Digital Converter 62
Sample and Hold Circuits
S&H circuits hold signal constant for conversion
A sample and a hold device (mostly switch and
capacitor)
Demands:
Small RC-settling-time (voltage over hold capacitor has to be
fast stable at < 1 LSB)
Exact switching point (else aperture-error)
Stable voltage over hold capacitor (else droop error)
No charge injection by the switch
Copyright Sill, 2008 Analog Digital Converter 63
6. Low Power ADC Design
What are the main components of power
dissipation?
How can each component be reduced?
What are the differences between power
and energy?

Copyright Sill, 2008 Analog Digital Converter 64
Power Dissipation
Two main components:
Dynamic power dissipation (P
dyn
)
Based on circuits activity
Square dependency on supply voltage V
DD
2

Dependent on clock frequency f
clk

Dependent on capacitive load C
load
Dependent on switching probability
P
dyn
= V
DD
2
C
load
f
clk



Static power dissipation (P
static
)
Constant power dissipation even if circuit is inactive
Steady low-resistance connections between VDD und GND
(only in some circuit technologies like pseudo NMOS)
Leakage (critical in technologies 0.18 m)
Copyright Sill, 2008 Analog Digital Converter 65
Low Power ADC Design
Reduction of V
DD
:
Highest influence on power (P ~ V
DD
2
)
Sadly, delay increases (t
d
~ 1/V
DD
)
Sadly, loss of maximal amplitude SNR goes down
Possible solutions:
Different supply voltages within the design
Dynamic change of V
DD
depending on required
performance
Reduction of f
clk
:
Dynamic change of f
clk

Copyright Sill, 2008 Analog Digital Converter 66
Low Power ADC Design contd
Reduction of C
load
:
C
load
depends on transistor count and transistor size,
wire count and wire length
Possible Solutions:
Reduction of amount evaluating components
Sizing of the design = all transistor get minimum
size to reach desired performance
Intelligent placing and routing

Copyright Sill, 2008 Analog Digital Converter 67
Low Power ADC Design contd
Reduction of :
Activity = possibility that a signal changes within one
clock cycle
Possible Solutions:
Clock gating no clock signal to inactive blocks
High active signals connected to the end of blocks


Asynchronous designs

Copyright Sill, 2008 Analog Digital Converter 68
Which ADC for Low Power?
If low speed: Dual Slope ADC
Area is independent of resolution
Less components
Problem: Counter
If medium / high speed: mixed solutions
Popular: pipelined ADC with SAR
Pipelined solutions allows reduction of V
DD
Long latency but high throughput
Copyright Sill, 2008 Analog Digital Converter 69
Power vs. Energy
Power consumption in Watts
Power = voltage current at a specific time point
Peak power:
Determines power ground wiring designs and
Packaging limits
Impacts of signal noise margin and reliability
analysis
Energy consumption in Joules
Energy = power delay (joules = watts * seconds)
Rate at which power is consumed over time
Lower energy number means less power to perform a
computation at the same frequency
Copyright Sill, 2008 Analog Digital Converter 70
Power vs. Energy contd
Watts

time

Power is height of curve

Watts

time

Energy is area under curve

Approach 1

Approach 2

Approach 2

Approach 1

Copyright Sill, 2008 Analog Digital Converter 71
Power vs. Energy: Simple Example
V
DD
I (each gray block) Delay Power Energy
Flash 1 V 1 A 1 ns 4 W 4 fJ
2L-Flash 1 V 1 A 2.5 ns 2 W 5 fJ
V
DD
V
in
I
V
in
V
DD
I
Flash
2L-Flash
Shaded blocks are ignored
Dissipation for one input signal:
Copyright Sill, 2008 Analog Digital Converter 72
Low Power ADCs Conclusion
There is no patent solution for low power ADCs!
Every solution depends on the specific task.
Before optimization analyze the problem:
Which resolution?
Which speed?
What are the constraints (area, energy, V
DD
, V
in
,)?
Which technology can be used?
Think also about unconventional solutions
(dynamic logic, asynchronous designs, ).

Copyright Sill, 2008 Analog Digital Converter 73
Open Questions
Is there another way to design low power ADCs?
Is it recommended to reduce the analog part and
put more effort in the digital part?
How do I achieve a high SNR with low power
ADCs?
Is it better to have only one block with high
frequency or many blocks with low frequency?
How can asynchronous designs help me?
How do I realize a low power ADC in sub-micron
technologies?
Copyright Sill, 2008 Analog Digital Converter 74
Basic ADC Literature
[All02] P. E. Allen, D. R. Holberg, CMOS Analog Circuit Design,
Oxford University Press, 2002
[Azi96] P.M. Aziz, H. V. Sorensen, J. Van der Spiegel, "An
Overview of Sigma-Delta Converters" IEEE Signal
Processing Magazine, 1996
[Eu07] E. D. Gioia, Sigma-Delta-A/D-Wandler, 2007

[Fi05] P. Fischer, VLSI-Design 0405 - ADC und DAC, Uni
Mannheim, 2005

[Man02] Mancini, Opamps for everyone, Texas Instr., 2002

[Joh97] D. A. Johns, K. Martin, Analog Integrated Circuit design,
John Wiley & Sons, 1997

[Tan00] S. Tanner, Low-power architectures for single-chip digital
image sensors, dissertation, University of Neuchatel,
Switzerland, 2000.
More Questions?
Copyright Sill, 2008 Analog Digital Converter 76
Signal Reconstruction
Continuous time (input signal):




Discrete (reconstructed by ADC):


/ 2
2
_
/ 2
( )
T
RMS ct
T
v t
V dt
T

=
}
v(t)
time
2
0
_
[ ]
n
i
RMS discrete
x n
V
n
=
=

x[n]
n
RMS: root mean square
Copyright Sill, 2008 Analog Digital Converter 77
Voltage supply reduction [Tan00]
For analog design, it is
shown that a voltage
supply reduction does not
always lead to a power
consumption reduction for
several reasons:
Threshold of MOS
transistors.
Loss of maximal amplitudes
(SNR degradation).
Limits of conduction in
analog switches.
Low speed of MOS
transistors.
Limited stack of transistors.
0
0.5
1
1.5
2
2.5
3
0 1 2 3 4 5 6
Supply Voltage [V]
P
o
w
e
r

D
i
s
s
i
p
a
t
i
o
n

[
m
W
/
M
S
/
s
]
Power consumption of 10-bit S-C
1.5 bit/stage pipelined ADCs in
function of the voltage supply.
[Tan00] S. Tanner, Low-power architectures for
single-chip digital image sensors, dissertation,
University of Neuchatel, Switzerland, 2000.