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Ladder Logic 12

Ladder diagrams use vertical rails and horizontal rungs to illustrate how electromechanical switches and relays are interconnected in a control system. Each rung represents a unique circuit branch between the power supply rails. Components include inputs, outputs, internal relays, and data registers. Programming uses bit instructions like examine if closed (XIC) and output energize (OTE) as well as timer and counter instructions. Logical continuity requires a path of true conditional instructions for the output instructions to occur. The PLC scans the ladder logic rungs from top to bottom.

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100% found this document useful (1 vote)
201 views

Ladder Logic 12

Ladder diagrams use vertical rails and horizontal rungs to illustrate how electromechanical switches and relays are interconnected in a control system. Each rung represents a unique circuit branch between the power supply rails. Components include inputs, outputs, internal relays, and data registers. Programming uses bit instructions like examine if closed (XIC) and output energize (OTE) as well as timer and counter instructions. Logical continuity requires a path of true conditional instructions for the output instructions to occur. The PLC scans the ladder logic rungs from top to bottom.

Uploaded by

mukesh2512
Copyright
© © All Rights Reserved
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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What is a Ladder ?

Ladder diagrams ( sometimes called "ladder logic ) are a type of electrical notation and symbology frequently used to illustrate how electromechanical switches and relays are interconnected. A Ladder diagram basically consists of two things:

Rails
Rungs

Components of Ladder
The two vertical lines in a ladder are called Rails" and are attach to opposite poles of a power supply.

Horizontal lines in a ladder diagram are called Rungs "


each one representing a unique parallel circuit branch between the poles of the power supply. PLC scans the rungs of ladder logic from left to right , starting from the top rung to the bottom rung.

001

002

003

Ladder Logic Basics


In Ladder logic, programming is done using registers. There are four kinds of registers:
Inputs and Outputs : are pointers to the actual terminal strip connectors on the PLC. If you energize an input, let's say 5th of group 1 of rack 1, then I:011/5 will have an on status Internal relays : are just about the same as Inputs and Outputs except that they don't point to any hardware. They just hold an ON / OFF value inside of the PLC's memory. Data registers : are used for data like integers and hexadecimal numbers as their addresses.

Logical Continuity
Each rung of ladder logic generally consists of two components. Conditional Instructions Output Instructions If there is a path of true conditional instructions, then the rung goes true and outputs occur.
SW-1 SW-2 MOTOR-1

SW-4

SW-5

LIGHT-2

Types of Instructions
Bit Instructions ( Input , Output , One Shot ) Timer Instructions Counter Instructions

Compare Instructions
Math Instructions Program Flow Instructions Block Transfer Instructions PID Instruction

Bit Instructions
Input Instructions:
XIC ( Examine If Close )

I:011

BIT STATUS ON

INSTRUCTION TRUE

15 I:011 OFF FALSE

15

Bit Instructions
Input Instructions:
XIC ( Examine If Open )

I:022

BIT STATUS ON

INSTRUCTION TRUE

15 I:022 OFF FALSE

15

Bit Instructions
Output Instructions:
OTE ( Output Energize ) Bit O:033/15 is high till the input conditions are true

O:033

RUNG STATUS TRUE

BIT STATUS ON

15 O:033 FALSE OFF

15

Bit Instructions
Output Instructions:
OTL ( Output Latch )

Bit O:033/15 remains high even after rung is false. OTL can only turn-on a bit.
O:033 RUNG STATUS TRUE BIT STATUS ON

L
15 O:033

FALSE

NO CHANGE

L
15

Bit Instructions
Output Instructions: OTU ( Output Unlatch )
U

Bit O:033/15 turns OFF when the rung is true. OTU can only turn-off a bit.
O:033 RUNG STATUS TRUE BIT STATUS OFF

U
15 O:033

FALSE

NO CHANGE

U
15

Bit Instructions
One Shot Instruction : ONS ( One Shot )

ONS

One-shot is used when it is required to enable the output only for one program scan upon a false to true transition of the conditions preceding the ONS instruction.
A unique address must be dedicated to each ONS instruction. ONS reference bit can be stored in a Binary or Integer file.

Bit Instructions
One Shot Instruction : Scan 1
ONS

Scan 2

ONS

Scan 3

ONS

Scan - 4

ONS

Logic Gates

Timer instructions
Timer Instruction Structure : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

T4:0 EN TT DN
Preset Value ( 16 Bit )

Internal Use Only

Accumulated Value ( 16 bit )

Structure No. ( 0-999 ) File No. ( 3-999 , Default = 4 ) File Type ( T )

Timer instructions
Timer Control Word :
.PRE Preset bit .ACC Accumulator bit .TT Timer timing Time base Specifies the value which the timer should reach before the processor sets/resets the .DN bit. Range : 0 32,767 Number of time increments the instruction has counted Counting starts from the value entered in this word. ( Typical value = 0 ) This bit is set the timer is timing 1 Sec : 0.01 Sec : Range = 32767 time base intervals ( 9.1 hours ) Range = 32767 time base intervals ( 5.5 minutes )

Timer instructions
Timer On Delay ( TON ) : This instruction is used to delay turning ON an output.

TON

TIMER ON DELAY Timer Time base Preset Accum

EN

DN

Timer instructions
TON Status Bits :

Rung False True True

ACC =0 <PRE =PRE

EN 0 1 1

TT 0 1 0

DN 0 0 1

Timer Reset Timing Timed out

Timer instructions
TON Example :
I:011 TON

12

TIMER ON DELAY Timer T4:0 Time base 1.0 Preset 3 Accum 0

EN

DN O:012

T4:0

TT T4:0

12
O:012

DN

13

Timer instructions
TON Example :
I:011 TON

12

TIMER ON DELAY Timer T4:0 Time base 1.0 Preset 3 Accum 1

EN

DN O:012

T4:0

TT T4:0

Sets o/p when timer is running

12
O:012

DN

13

Timer instructions
TON Example :
I:011 TON

12

TIMER ON DELAY Timer T4:0 Time base 1.0 Preset 3 Accum 2

EN

DN O:012

T4:TT

TT T4:0

Sets o/p when timer is running

12
O:012

DN

13

Timer instructions
TON Example :
I:011 TON

12

TIMER ON DELAY Timer T4:0 Time base 1.0 Preset 3 Accum 3

EN

DN O:012

T4:0

TT T4:0

12
O:012

DN

Sets o/p when timer is done timing

13

Timer instructions
TON Example :
I:011 TON

12

TIMER ON DELAY Timer T4:0 Time base 1.0 Preset 3 Accum 3

EN

DN O:012

T4:0

TT T4:0

12
O:012

DN

13

Timer instructions
Timer Off Delay ( TOF ) : This instruction is used to delay turning OFF an output.

TOF

TIMER ON DELAY Timer Time base Preset Accum

EN

DN

Timer instructions
TOF Status Bits :

Rung True False False

ACC =0 <PRE =PRE

EN 1 0 0

TT 0 1 0

DN 1 1 0

Timer Reset Timing Timed out

Timer instructions
TOF Example :
I:011 TOF

12

TIMER ON DELAY Timer T4:0 Time base 1.0 Preset 3 Accum 0

EN

DN O:012

T4:0

TT T4:0

12
O:012

DN

Sets o/p when timer is not timing

13

Timer instructions
TOF Example :
I:011 TOF

12

TIMER ON DELAY Timer T4:0 Time base 1.0 Preset 3 Accum 1

EN

DN O:012

T4:0

TT T4:0

Sets o/p when timer is timing

12
O:012

DN

Sets o/p when ACC < PRE

13

Timer instructions
TOF Example :
I:011 TOF

12

TIMER ON DELAY Timer T4:0 Time base 1.0 Preset 3 Accum 2

EN

DN O:012

T4:0

TT T4:0

Sets o/p when timer is timing

12
O:012

DN

Sets o/p when ACC < PRE

13

Timer instructions
TOF Example :
I:011 TOF

12

TIMER ON DELAY Timer T4:0 Time base 1.0 Preset 3 Accum 3

EN

DN O:012

T4:0

TT T4:0

Resets o/p when timer is done timing

12
O:012

DN

Resets o/p when ACC = PRE

13

Timer instructions
TOF Example :
I:011 TOF

12

TIMER ON DELAY Timer T4:0 Time base 1.0 Preset 3 Accum 0

EN

DN O:012

T4:0

TT T4:0

12
O:012

DN

13

Timer instructions
Retentive Timer ( RTO ) : A Retentive Timer lets the timer stop without resetting the accumulated value.

RTO

TIMER ON DELAY Timer Time base Preset Accum

EN

DN

Timer instructions
RTO Status Bits :

Rung False True False True False

ACC =0 <PRE <PRE =PRE =PRE

EN 0 1 0 1 0

TT 0 1 0 0 0

DN 0 0 0 1 1

Timer Reset Timing Partially timed Timed out Timed out

Timer instructions
RTO Example :
I:011 RTO

12

TIMER ON DELAY Timer T4:0 Time base 1.0 Preset 5 Accum 0

EN

DN O:012

T4:0

TT T4:0

12
O:012

DN

13

Timer instructions
RTO Example :
I:011 RTO

12

TIMER ON DELAY Timer T4:0 Time base 1.0 Preset 5 Accum 1

EN

DN O:012

T4:0

TT T4:0

Sets o/p when timer is timing

12
O:012

DN

13

Timer instructions
RTO Example :
I:011 RTO

12

TIMER ON DELAY Timer T4:0 Time base 1.0 Preset 5 Accum 2

EN

DN O:012

T4:0

TT T4:0

Sets o/p when timer is timing

12
O:012

DN

13

Timer instructions
RTO Example :
I:011 RTO

12

TIMER ON DELAY Timer T4:0 Time base 1.0 Preset 5 Accum 2

EN

DN O:012

T4:0

TT T4:0

Resets o/p when timer is not timing

12
O:012

DN

13

Timer instructions
RTO Example :
I:011 RTO

12

TIMER ON DELAY Timer T4:0 Time base 1.0 Preset 5 Accum 3

EN

DN O:012

T4:0

TT T4:0

Sets o/p when timer is timing

12
O:012

DN

13

Timer instructions
RTO Example :
I:011 RTO

12

TIMER ON DELAY Timer T4:0 Time base 1.0 Preset 5 Accum 4

EN

DN O:012

T4:0

TT T4:0

Sets o/p when timer is timing

12
O:012

DN

13

Timer instructions
RTO Example :
I:011 RTO

12

TIMER ON DELAY Timer T4:0 Time base 1.0 Preset 5 Accum 5

EN

DN O:012

T4:0

TT T4:0

12
O:012

DN

Sets o/p when timer is done timing

13

Timer instructions
RTO Example :
I:011 RTO

12

Rung is false but ACC is not reset


T4:0

TIMER ON DELAY Timer T4:0 Time base 1.0 Preset 5 Accum 5

EN

DN O:012

TT T4:0

12
O:012

DN

13

Timer instructions
RTO Example :
I:011 RTO 12

TIMER ON DELAY Timer T4:0 Time base 1.0 Preset 5 Accum 5

EN

DN O:012

T4:0

TT T4:0

12 O:012

DN I:011

13 T4:0

RES
13

Timer reset required to reset ACC

Timer instructions
RTO Example :
I:011 RTO 12

ACC reset
T4:0

TIMER ON DELAY Timer T4:0 Time base 1.0 Preset 5 Accum 0

EN

DN O:012

TT T4:0

12 O:012

DN I:011

13 T4:0

RES
13

Counter Instructions
Counter Instruction Structure : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

C5:0 CU CD DN OV UN
Preset Value ( 16 Bit ) Accumulated Value ( 16 bit )

Structure No. ( 0-999 ) File No. ( 3-999 , Default = 5 ) File Type ( C )

Counter Instructions
Counter Control Word :
.PRE Preset bit
.ACC Accumulator bit .CU Count-up enable .CD Count-down enable .DN Done bit .OV Overflow bit .UN Underflow bit

Specifies the value which the counter should reach before the processor sets/resets the .DN bit. Range : 32,767 to + 32,767
Number of false-true transitions instruction has counted Bit SET when rung containing count-up instruction is true Bit SET when rung containing count-down instruction is true Bit SET when PRE = ACC Bit SET when counter has counted above upper limit +32,767 Bit SET when counter has counted below lower limit - 32,767

Counter Instructions
Counter Value Range :

0
-1 1

-32,767 UV Set

+32,767 OV Set

Counter Instructions
Count-up ( CTU ) :
Each time rung goes from false true ACC value increases by 1
CTD

Count Down Counter Preset Accum

EN

DN

Counter Instructions
CTU Status - Bits :

Rung

ACC

CD

DN

True
False

<PRE
<PRE

1
0

0
0

True
False

>=PRE
>=PRE

1
0

1
1

Counter Instructions
Count-down ( CTD ) :
Each time rung goes from false true ACC value decreases by 1
CTD

Count Down Counter Preset Accum

EN

DN

Counter Instructions
CTD Status - Bits :

Rung

ACC

CD

DN

True
False

<PRE
<PRE

1
0

0
0

True
False

>=PRE
>=PRE

1
0

1
1

Counter Instructions
Counter Reset ( RES ) :
Reset instruction is an output instruction that resets a timer or counter. It is set when its rung is true. Address of reset instruction is the address of timer/counter it is resetting.

RES

Compare Instructions
Equal To ( EQU ) :
EQU is used to test whether two value are equal. If source A is equal to Source B than output is energized.

EQU

EQUAL Source A Source B

O:012
N7:9 N7:10

12

Compare Instructions
Greater Than Or Equal To ( GEQ ) :
GEQ is used to test whether Source A is greater than Source B. Source A or Source B can be value or addresses that contain values.
GEQ

Greater Than Or Equal Source A N7:9 Source B N7:10

O:012

12

Compare Instructions
Greater Than ( GRT ) :
GRT is used to test whether Source A is greater than Source B. Source A or Source B can be value or addresses that contain values.
GRT

Greater Than Source A Source B

O:012
N7:9 N7:10

12

Compare Instructions
Less Than Or Equal To ( LEQ ) :
LEQ is used to test whether Source A is less than or equal to Source B. Source A or Source B can be value or addresses that contain values.
LEQ

Less Than Or Equal Source A N7:9 Source B N7:10

O:012

12

Compare Instructions
Less Than ( LES ) :
LES is used to test whether Source A is less than Source B. Source A or Source B can be value or addresses that contain values.

LES

Less Than Source A Source B

O:012
N7:9 N7:10

12

Compare Instructions
Limit Test ( LIM ) :
LIM is an input instruction that is used to test for value inside of outside of a specified limit. When the value being monitored is within limit the output goes true. Low / High Limit can be a value or addresses that contains values
LIM

Limit Test ( CIRC) Low Limit N7:10 Test N7:11 High Limit N7:12

O:012

12

Compute Instructions
Compute instructions evaluate arithmetic operations using an expression or a specific arithmetic instruction. Following are commonly used math instructions:

CPT : Evaluate an expression


ADD : Add two values SUB : Subtract two values DIV : Divide one value by other MUL : Multiply two values

Compute Instructions
Arithmetic Status Flags: The arithmetic status flags are stored in Bits-0, 1, 2 & 3 of Word 0 of the processor status file.
S:0/0 CARRY ( C ) ZERO ( Z ) SIGN (S ) Sets when Carry is generated Sets if result is zero Sets if result is negative

S:0/1
S:0/2 S:0/3

OVERFLOW ( V ) Sets when overflow is generated

You can use either Integer or Floating point values. If source is floating point , Destinations should also be a floating point address else result will be rounded off If you enter BCD or ASCII values, processor treats those values as integers.

Compute Instructions
Compute Instruction ( CPT ):

Compute instruction is an output instruction. Its operation is defined by the expression given in the instruction. This instruction can perform various operations other than computing like:

Copy data from one address to another


Clear data of the destination address
CPT

Convert data type at source to data type specified at destination

COMPUTE
Destination Expression

Compute Instructions
Valid CPT Operators:

Enhanced PLC processors support more operators ( Sine, Cosine, Tangent, AND, OR, XOR etc. )
Type Copy Clear Arithmetic Operator None None + * SQR Description Copy from A to B Set a value to zero Add Subtract Multiply Negate SQUARE ROOT Example Enter Source in Expression and Desti. in destination Enter 0 for expression 2+3 11 4 12 * 3 24 I 2 - N7:0 SQR N7:2

I ( vertical bar ) Divide

Compute Instructions
CPT - Example:
CPT

I:012

COMPUTE

Destination

N7:21

12

Expression (N7:5 I 5 ) I ( N7:6 )

If input I:012/12 is SET divide value in N7:5 by 5 and divide the result by value in N7:6. Move the final result to destination address N7:21.

Compute Instructions
Addition ( ADD ):

When input condition is true adds Source A and Source B and stores the result in destination address. Status flags are set in status file as defined earlier.
I:012
ADD

ADD

12

Source A Source B
Destination

N7:2 N7:3
N7:21

If input I:012/12 is SET add values in N7:2 & N7:3 and store the result in N7:21

Compute Instructions
Subtract ( SUB ):

When input condition is true subtract Source B from Source A and stores the result in destination address. Status flags are set in status file as defined earlier.
I:012
SUB

SUBTRACT

12

Source A Source B
Destination

N7:2 N7:3
N7:21

If input I:012/12 is SET subtract value in N7:3 from value in N7:2 and store the result in N7:21

Compute Instructions
Divide ( DIV ):

When input condition is true divide Source A from Source B and stores the result in destination address. Status flags are set in status file as defined earlier.
I:012
DIV

DIVIDE

12

Source A Source B
Destination

N7:2 N7:3
N7:21

If input I:012/12 is SET divide value in N7:2 by value in N7:3 and store the result in N7:21

Compute Instructions
Multiply ( MUL ):

When input condition is true divide Source A from Source B and stores the result in destination address. Status flags are set in status file as defined earlier.
I:012
MUL

MULTIPLY

12

Source A Source B
Destination

N7:2 N7:3
N7:21

If input I:012/12 is SET multiply value in N7:2 and value in N7:3 and store the result in N7:21

Compute Instructions
Clear ( CLR ):

When input condition is true CLR sets all the bits of the destination word to zero.
CLR

I:012

CLEAR Destination N7:21

12

If input I:012/12 is SET , set all bits of word N7:21 to zero

Move Instructions
Move ( MOV ):

MOV instruction is a output instruction that copies the source address to the destination address. The instruction moves data each scan till the rung is true.
The source and destination data should be same as this instruction does not perform a conversion.
I:012
MOV

MOVE Source N7:0 N7:21

12

Destination

If input I:012/12 is SET value in N7:0 is moved to N7:21

Move Instructions
Masked Move ( MVM ): MOV instruction is a output instruction that copies the source address to the destination address while allowing some portion of data to be masked. The instruction moves data each scan till the rung is true. You can use MVM to copy I/O image, Binary or Integer values. MASK : is an address or Hexadecimal value that specifies which bit to pass or block. ( Set 1 to mask the data ; Set 0 to block ) Data passed from masked bit overwrites the corresponding bits in the destination address. Other bits remain unchanged.

Move Instructions
MVM Example:
MVM

MASKED MOVE Source N7:0 Mask 1111000011110000 Destination N7:21

N7:21 Before move N7:0 Source

Mask F0F0
N7:21 After move

0 1

Program Flow Instructions


Program flow instructions change the flow of ladder program execution. Following are commonly used program flow instructions

JMP
Jump (JMP) : When Jump instruction is true it lets processor skip rungs.

LBL
Label (LBL ) : Label instruction is the target of the Jump instruction that has same label number. LBL should be the first instruction on the rung.

Program Flow Instructions


Always False (AFI) :
The AFI instruction is a input instruction that is used to make a rung false when inserted in the condition side of the rung.

AFI

Block Transfer Instructions


Block-transfer instructions are used to transfer upto 64 words of data to/from a block transfer module in a local/remote I/O chassis.
Block-transfer Write (BTW) : is used when you want to transfer data to the block-transfer module. When the rung goes true the instruction tells the processor to write data in the the data file specified to the specified rack/group/module address Block-transfer Read (BTR) : is used when you want to receive data from the block-transfer module. When the rung goes true the instruction tells the processor to read data from the rack/group/module address and store it in the data file

Block Transfer Instructions


BTW and BTR Structure:
BTW

BLOCK TRANFR WRITE Rack Group Module Control Block Data file Length Continuous

EN

DN

Block Transfer Instructions


Parameters of Block-transfer instructions:
Rack Group I/O rack no. ( 00-17 octal for PLC-5/40) of the I/O chassis in which the module is placed I/O group no. (0-7) which indicates the position of the module in the I./O chassis

Module
Control Block Data File Length Continuous

Slot no. within the group


6 word block transfer file (BT) or 5 word Integer file that controls the instruction operation Address of the integer file from/to which processor write/read the data Number of words to be transferred ( 1 to 64 ) Mode of operation YES instruction enabled once rung is true NO instruction enabled each time rung goes true

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