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Assignment #2 is posted. It is due on Monday, 18
Apr., 2011, at the beginning of class.
Lab3 and Lab4 are posted.
Eng. Mohamed Eissa will take the last 15-20 min of
todays class to present Lab3 and Lab4.
Tutorials and labs.
Lecture slides and videos.
Terms
Essential Computer
CPU + Memory
Peripheral devices
Any device attached to a computer in order to increase
its functionality.
External: printers, scanners, microphones, speakers, etc
Internal: disk drives, CD-ROM drives, modem, etc
Input-only: keyboard and mouse
Output-only: printers
Input and output: writable CD-ROM.
I/O (Input/Output)
The transfer of data to/from a computer from/to a
peripheral device (done by a program, operation, or a
device).
Input: from a device to the computer
Output: from the computer to a device.
Input/Output Problems
Wide variety of peripherals
Different methods of operation (H/W).
Delivering different amounts of data
At different speeds (and different from
CPU and memory)
In different formats (e.g., word length)

Solution?

I/O modules
I/O Module
Interface to CPU and Memory
Interface to one or more peripheral devices
Types of I/O Devices
Human readable
Screen, printer, keyboard
Machine readable
Magnetic disk, tape
Communication
Modem
Network Interface Card (NIC)

External Device
External Device (Peripheral)
Control Signals
Send data to module,
receive data from module,
send status, position disk
head.
Status signals
READY, NOT READY
Buffer: temporarily hold
data being transferred,
8-16 bits is common.
Transducer: energy-
electrical signals.
Control logic
Controls operation.
I/O Module
To/from computer
Computer
Outside world
Keyboard/Monitor, and Disk Drive
ASCII
Printable and control (e. g., carriage return).
Keyboard
A key is pressed.
Transducer translates signal into ASCII.
ASCII is transmitted to I/O module in the computer.
Text can be stored as ASCII in the computer.
Monitor
On output, computer sends ASCII to I/O module. I/O
module sends ASCII to external device (monitor).
Transducer at the monitor sends electronic signals to
display the character.
Disk Drive
Transducer converts magnetic patterns to/from bits.
Head can be moved in and out across disks surface.
Lecture 6
Chapter 7. Input/Output (Cont.)
Functions of I/O Module
1. Control & Timing.
2. CPU Communication.
3. Device Communication.
4. Data Buffering.
5. Error Detection.
1. Control & Timing - Input Operation
Common CPU, memory, and bus timing is
needed
1. CPU checks I/O module device status.
2. I/O module returns status.
3. If ready, CPU requests data transfer (command
to I/O module).
4. I/O module gets data from external device.
5. I/O module transfers data to CPU.
Variations for output, DMA, etc.
Bus arbitration.
2. CPU Communication
Decode command
I/O module accepts commands from CPU on control lines.
e.g., SEEK track number (command + parameter on data
lines) for a disk drive.

Recognize address
One unique address for each peripheral it controls.

Exchange data
Between CPU and device over the data bus.

Report status
BUSY, READY, or some error conditions.
3. Device Communication
I/O module must be able to do device
communication.
Commands
Status information.
Data.
4. Data Buffering (Speed Mismatch)
5. Error Detection
Mechanical and electrical malfunctions
Report to CPU.
e.g., paper jam, bad disk track.
Bit pattern changes
Parity bit (ASCII).
I/O Module
Status register: holds device status or accepts control info from CPU.
Some control lines may be used by the module for bus arbitration.
If module controls more than one device, it has a set of unique
addresses.
I/O Module Decisions
Hide or reveal device properties to CPU.
Support multiple or single device.
Control device functions or leave for CPU.
Also O/S decisions
e.g. Unix treats everything it can as a file
I/O channel (I/O processor)
I/O module takes most of work.
Mainframe.
I/O controller (device controller)
Primitive I/O module.
PC.
Input Output Techniques
Programmed.
Interrupt driven.
Direct Memory Access (DMA).
Programmed I/O
CPU (program) has direct control over I/O
Sensing status
Read/write commands
Transferring data
CPU waits for I/O module to complete
operation
Wastes CPU time
CPU issues a command to the I/O module.
I/O module performs operation.
I/O module sets status bits.
CPU checks status bits periodically.
I/O module does not inform CPU directly.
I/O module does not interrupt CPU.
CPU may wait or come back later.
I/O Commands
CPU executes an I/O-related instruction.
CPU issues address
Identifies module (& device if >1 per module)
CPU issues command
Control - telling module what to do
e.g. spin up disk
Test - check status
e.g. power? Error?
Read/Write
Module transfers data via buffer from/to device
With programmed I/O, there is a one-to-one
mapping between I/O instructions and I/O
commands.
Addressing I/O Devices
Under programmed I/O, data transfer is very like
memory access (CPU viewpoint).
Each device given unique identifier.
CPU commands contain identifier (address).
I/O Mapping
Memory mapped I/O
Devices and memory share the same address
space.
I/O looks just like memory read/write.
No special instructions for I/O
Large selection of memory access instructions
available.
Isolated I/O
Separate address spaces
Need I/O or memory select lines
Special instructions for I/O
Limited set
I/O Mapping - Example
Interrupt-Driven I/O
Overcomes CPU waiting
No repeated CPU checking of device
I/O module interrupts when ready
Interrupt Driven I/O
Basic Operation
CPU issues read command
I/O module gets data from
peripheral whilst CPU does
other work
I/O module interrupts CPU
CPU requests data
I/O module transfers data

CPU Viewpoint
Issue read command.
Do other work.
Check for interrupt at end of each instruction cycle.
If interrupted:
Save context (registers).
Process interrupt.
Fetch data & store
See Operating Systems notes.
Identifying Interrupting Module
How do you identify the module issuing the interrupt?
Different line for each module
PC
Limits number of devices
Software poll
CPU asks each module in turn
Slow
Daisy Chain or Hardware poll
Interrupt Acknowledge sent down a chain
Module responsible places vector on bus
CPU uses vector to identify handler routine
Bus Master
Module must claim the bus before it can raise interrupt
e.g. PCI & SCSI
Multiple Interrupts
How do you deal with multiple interrupts?
i.e. an interrupt handler being interrupted
Each interrupt line has a priority.
Higher priority lines can interrupt lower priority lines.
If bus mastering only current master can interrupt.
Example - PC Bus
80x86: one interrupt line.
8086 based systems: 1
82C59A intrpt controller.
82C59A: 8 intrpt lines.
Sequence of events
82C59A accepts
interrupts
82C59A determines
priority
82C59A signals 8086
(raises INTR line)
CPU Acknowledges
82C59A puts correct
vector on data bus
CPU processes
interrupt.
Reading Material
Stallings, chapter 7, pages 222-233