Unit 1

Synchronous
sequential network
Introduction
Fig shows a general model of a sequential network.
Memory provides information about the past history
of inputs.
In physical system, flip-flops are used for holding
information.
The outputs of the flip-flops denote the present state
of the system.
The inputs to the memory box are associated with the
next state.
Synchronous Sequential Networks

In this model the output is dependent on
present input and also past output.
Fig. Sequential Network Model
Cont..
This is classified into synchronous and asynchronous.
synchronous
the behavior of the system is determined by the
present state values and external input signals at
discrete instant of time.
Memory elements are clocked flip-flops.
The maximum operating speed of the clock depends
on the time delays involved.
Easier to design.
In asynchronous the input signal change affects the
network behavior
Cont.
asynchronous
the input signal change affects the network
behavior
The memory elements are unclocked flip-flops
or time delay elements.
It can operate faster than synchronous circuits
More difficult to design compared to
synchronous circuits

Clocked Synchronous Sequential Network


Cont..
The clock signal is a periodic waveform having one
positive edge and one negative edge during each
period.
One part of he clock signal has the value of logic 1,
whereas the other part have logic value of 0.
Control signal is applied to the clocked flip-flops.
Master clock is applied to provide synchronization
and to avoid timing problems.
The clock signal is applied simultaneously to all flip-
flops.
Mealy model
Its output is a function of present state as well
as present input.
Input changes may affect the output of the
circuit
It requires less number of states for
implementing same function.
Mealy Model
Outputs are only a function of the external inputs and the present state. Hence
it is given by
Z = g(X,Q)
Mealy model of a clocked synchronous sequential network
Moore model
Its output is a function of present state only.
Input changes does not affect the output
Moore model requires more number of states
for implementing the same function.
Moore Model
Outputs are only a function of the present state. It is given as follows
Z = g(Q)
Moore model of a clocked synchronous sequential network
Algorithmic State Machine

Describing the behavior of the Algorithmic State
Machine (ASM)in the form of block diagram
structure which is similar to flow charts used in the
software design.this flowchart is called as ASM
charts.
The difference between these two flow charts is time
interpretation.
software flow charts are used to describe the
sequence of events that occur.
Asm charts describe a seauence of time intervals.

Cont..
An ASM chart is a method of describing the
sequential operations of a digital system.
The ASM diagram is easy to understand.
ASM charts consists of three baic components
1) The state box
2) The decision box
3) The conditional box
Cont..
State box:
The output of the state is indicated inside the
rectangle box
It has single entry path to state box and a single exit
path from a state box
State box
Cont..
State name:
The name of the state is indicated inside the
circle and the circle is placed in the top left
corner or the name is placed without the circle.

State Name
Cont.
Decision box
It has single entry path and two exit paths
The basic function of the decision box is to provide next-state
alternative and conditional outputs.
Conditional outputs based on logic value of the boolean
exprression.
The boolean expression appears as the entry in the decision
box.
The result of the decision box is logic 0 (false) and logic
1(true), there exits two exit paths.
Exit paths can lead to another state box, decision or
conditional box
Cont
It is denoted by a diamond symbol.
Diamond indicates that the stated condition
expression is to be tested and the exit path is
to be chosen accordingly.
Decision box
Cont.
Conditional output box:
Conditional output box has a single entry path from a
decision box and a single exit path to another decision
box or a state box.
This box provides listing called the conditional output
list
It is denoted by oval shaped symbol.
An oval denotes the output signals that are of Mealy
type.
These outputs depend on the state and the inputs of
the FSM.
Cont.
The conditional output box is preceded by a decision
box.
It is independent of time.

Conditional output box
Analysis of Clocked Synchronous
Sequential Networks
There are the two main reasons for the analysis
1)To determine Tabular description of sequential networks. It
is very useful when sequential networks are to be designed.
2)To determine the behavior of clocked signal. It has the
following steps.
Here the clock signals are applied simultaneously to the flip-
flops for synchronization.
Positive edge triggered flip-flops are used for the memory
portion of the network.
The flip-flops change state only at the leading edge of the
clock signal.
D flip-flop is used for the analysis.
Cont.
The figure shown corresponds to a Mealy network
Here the present state of the sequential networks corresponds
to the signals at the output terminals of the flip-flop.
These signals are fed back to the combinational logic that
precedes the flip-flop input terminal.
Logic diagram for example.
Basic design steps
These are the steps for the design of the clocked
synchronous sequential circuits
First obtain the state table from the given circuit
information such as state diagram and a timing
diagram.
The number of states can be reduced by state
reduction techniques
Assign binary values to each state in the state table
Determine the number of flip-flops needed and assign
a letter symbol to each of it.
Cont..
Choose the type of the flip-flop to be used.
From the state table derive the circuit
excitation and output tables
Flip-flop input functions and circuit output
functions can be obtained using k-map or other
simplification method
Draw the logic diagram
Cont
It has the following methods
Excitation and Output Expressions
Transition Equations
Transition Tables
Excitation Tables
State Tables
State Diagrams
Network Terminal Behavior

EXCITATION AND OUTPUT EXPRESSIONS
Algebraic expressions served as mathematical expressions for sequential
networks.
In order to write the algebraic expressions for sequential networks, assign
present state variable to each of the output terminals of the flip-flop.
The excitation to the flip-flops in figure can be expressed as follows.



2 1 2
1 Q Q Q x D

D
2
xQ
1
Q
1
Q
2

z xQ
1
xQ
1
Q
2
Transition Equations
To convert excitation expressions into next state expression it is
necessary to use the characteristics equation of the flip-flop.
In order to obtain the algebraic equation of the next state of the flip-
flop, substitute the excitation expressions for a flip-flop into its
characteristic equation.
For the above example, the next state of the flip-flop are give by
Q1* = D1
Q2* = D2
now substituting the values of D1 and D2 the equation becomes as follows
2 1 2
* 1 Q Q Q x Q
2 1 1 2
* Q Q Q x Q
Present state
(Q
1
Q
2
)
Next state
(Q
1
+
Q
2
+
)
Output
(z)
Input (x) Input (x)
0 1 0 1
00
01
10
11
10
11
10
00
01
11
00
00
0
0
1
1
1
0
0
0
Transition Tables
The transition table is the tabular representation of the transitions and
output equations. The transition table for the above e.g. is shown

Excitation Tables:
The excitation table consists of three section: the present
state section, the excitation state and the output section.

Present state
(Q
1
Q
2
)
Excitation
(D
1
D
2
)
Output
(z)
Input (x) Input (x)
0 1 0 1
00
01
10
11
10
11
10
00
01
11
00
00
0
0
1
1
1
0
0
0
Cont.
The present state section lists the combination
of the of values of state variables.
The output section corresponds to the
evaluation of the output expressions of the
networks.
The excitation section consists of one column
for each combination of values of the external
input variables.
State tables
Alpha numeric symbols can be assigned to represent
the states. when this relabeling is done to the
transition table, the resulting table is called as state
tables.
The state table consists of three sections
The present state
The next state
The output section
The present state and output section are obtained
by replacing the binary code.
The output section is identical with the transition
tables.
State Table
Present state Next state Output (z)
Input (x) Input (x)
0 1 0 1
00A
01B
10C
11D
C
D
C
A
B
D
A
A
0
0
1
1
1
0
0
0
State Table
Present state Next state, Output (z)
Input (x)
0 1
A
B
C
D
C,0
D,0
C,1
A,1
B,1
D,0
A,0
A,0
State diagram
Graphical representation of the state table is referred
to as the state diagram.
Each state is represented by a node.
Direct branches connect the nodes to indicate the
transition between the states.
For mealy sequential circuits the output appears on
the directed branches along with the external inputs
For Moore, the outputs are included with the
associated states
State diagram
Network Terminal Behavior
The objective is to obtain the time response for
a sequence of inputs.
It is obtained from the logic diagram by tracing
the signals, the state table or state diagram.
Input sequence x = 0 0 1 1 0 1 1 1 0 1
State sequence = A C C A B D A B D A B
Output sequence = 0 1 0 1 0 0 1 0 1 1
Timing diagram
The analysis procedure