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Meta Stability

Metastability occurs when there are setup and hold time violations in a flip-flop, causing its output to enter an unpredictable quasi-stable state. Adding multiple flip-flops in series can help avoid metastability by allowing each flip-flop time to resolve before the next samples its output. The mean time between failures (MTBF) gives the average time interval between successive failures and can be used to determine the probability of metastability for different types of flip-flops under varying clock frequencies and input transition rates.

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Sahil Sharma
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124 views

Meta Stability

Metastability occurs when there are setup and hold time violations in a flip-flop, causing its output to enter an unpredictable quasi-stable state. Adding multiple flip-flops in series can help avoid metastability by allowing each flip-flop time to resolve before the next samples its output. The mean time between failures (MTBF) gives the average time interval between successive failures and can be used to determine the probability of metastability for different types of flip-flops under varying clock frequencies and input transition rates.

Uploaded by

Sahil Sharma
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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By-

Abhinav Vishnoi
Assistant Professor
Lovely Professional University

Whenever there are setup and hold time violations in any flip-flop, it
enters a state where its output is unpredictable: this state is known as
metastable state(quasi stable state).
Metastability can occur, if the setup (t
SU
), hold time (t
H
), or clock pulse
width (t
PW
) of a flip-flop is not met.
A problem for asynchronous systems or events.
Three possible symptoms:
Increased CLK Q delay.
Output a non-logic level
Output switching and then returning to its original state.
Theoretically the amount of time a device stays in the metastable state
may be infinite.
At the end of metastable state, the flip-flop settles down to either '1' or
'0'.

metastable happen when two inputs such as data and clock or
clock and reset are changing at about the same time
The only safe way:
use a synchronizer
3
clk
d
Q (output)
Meta-stable data
Setup & hold
violation
Reason for Metastability
whenever setup and hold time violation
When the input signal is an asynchronous signal.
When the clock skew is too much (rise and fall time are more than the
tolerable values).
When interfacing two domains operating at two different frequencies or at
the same frequency but with different phase.
When the combinational delay is such that flip-flop data input changes in the
critical window (setup+hold window).
To Avoid Metastability

Make sure the clock period is long enough to allow for the result out
To add one or more successive synchronizing flip-flops to the synchronizer.
This approach allows for an entire clock period for metastable events in the
first synchronizing flip-flop to resolve thems elvesion of quasi-stable states
MTBF is Mean time between failure, Well MTBF gives us information
on how often a particular element will fail or in other words, it gives
the average time interval between two successive failures.

MTBF is a figure of merit related to metastability

Fin: Data Frequency
Fclk: Clock Frequency
T
d
: Flip Flop critical time window (tsu+th)

MTBF gives us information on how often a particular element will fail or it
gives the average time interval between two successive failures
A flip-flop uses to synchronize two signals in this application cannot expect
the maximum delays stated in the data sheets
it is necessary to know how long to wait after the clock pulse before the data
can be evaluated.
A special test circuit is needed to determine the MTBF and the time (tx)

The clock signal (fCLK2) delayed by the time (tx) by delay line DL2
it is possible to
determine the
time between
two failures as
a function of
the time (tx)

Semi-
Logrithmic
graph
Higher the frequency the lower is the probability that a metastable
state will occur the probability increases for lower frequencies
Metastable response of a component for any frequencies
settling time
Td and T describe the metastable response of the circuit
Constant T determines the slope of the lines
exp( * )
* *
T tx
MTBF
fclk fin td

Family T/n
s
Td
Std-
TTL
0.7
4
2.9*10^-4
LS 0.7
4
4.8*10^-3
S 0.3
6
1.3*10^-9
ALS 1.0 8.7*10^-6
AS 4.0 1.4*10^3
F 9.2 1.9*10^8
BCT 1.5
1
1.14*10^-6
ABT 3.6
1
33*10^-3
HC 0.5
5
1.46*10^-6
AC 2.8 1.1*10^-4
Type of flip-flop SN74ALS74
fin = 10 kHz / fclk = 25 MHz / tsu
= 15 ns
Td = 8.7 us

error rate is too much high
To reduce MTBF use circuit that exhibit a much shorter settling time
that leave the metastable state faster. For SN74AS series in which the
constant (T) is high
fin = 10 kHz / fclk = 25 MHz / tsu = 15 ns / Td =
1.4*10^3 / T= 4.0

exp(4*25 )
25 *10 *1.4*10^ 3
ns
MTBF
MHz KHz

mean time between two failures (MTBF) is 2.4 x 10^21


years
Adding a second Flip Flop to the design will reduce the chance of the
output going Metastable.
The output from the first flip flop may go valid before the second flip
flop is clocked.
It connect asynchronous input to the rest of system
Whenever there is signal transfer between two systems operating at
different frequencies or same frequency with different phases,
synchronizer is used as an interface so that signal from transmitter
block is reliably interpreted by the receiver.
This block ensures that there is no metastability for a target MTBF.

There are two inputs the clock C and the
asynchronous signal D and one output
the synchronised signal D.
The two input signals interact
asynchronously modelled roughly by
operating frequencies f1 and f2
A simple synchronizer comprises two flip-flops in series
without any combinational circuitry between them. This
design ensures that the first flip-flop exits its metastable
state and its output settles before the second flip-flop
samples it
The synchroniser is expected to provide a defined logic level
(0 or l) within a bounded decision time after D otherwise a
synchronisation failure has occured.
The second flip-flop receives the output signal of the first stage after one
clock period and can go into a metastable state only if its input conditions
are violated.

the output of the first flip-flop is still metastable during its setup and hold
time. So the critical input frequency fin(2) of the second stage is calculated
from the reciprocal of the mean time between two failures of the first stage:
one SN74ALS74 flip-flop, the MTBF was 54 minutes. Again, assuming
that the second flip-flop is sampled after 25 ns
Mean Time Between Failure (MTBF) of a particular flip-flop in the context of a
given clock rate and input transition rate is 33.33 seconds then the MTBF of
two such flip-flops used to synchronize the input would be (33.33* 33.33) =
18.514 Minutes

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