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44 views

Electromagnetic

electromagnetic

Uploaded by

lim hy
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
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Convolution Codes

Introduction
Convolutional codes map information to code

bits sequentially by convolving a sequence of


information bits with generator sequences
A
convolutional
encoder
encodes
K
information bits to N>K code bits at one time
step
Convolutional codes can be regarded as
block codes for which the encoder has a
certain structure such that we can express
the encoding operation as convolution

Encoder Structure
A convolutional code introduces redundant

bits into the data stream through the use of


linear shift registers as shown in Figure 1.

Figure 1

The information bits are input into shift registers and the

output encoded bits are obtained by modulo-2 addition


of the input information bits and the contents of the shift
registers.
The connections to the modulo-2 adders were developed
heuristically with no algebraic or combinatorial
foundation.
The code rate r for a convolutional code is defined as

where k is the number of parallel input information bits


and n is the number of parallel output encoded bits at
one time interval.
The constraint length K for a convolutional code is
defined as
where m is the maximum number of stages (memory
size) in any shift register.

The

shift registers store the state information of the


convolutional encoder and the constraint length relates the
number of bits upon which the output depends.

For the convolutional encoder shown in Figure 1, the code

rate r=2/3, the maximum memory size m=3, and the


constraint length K=4.
A convolutional code can become very complicated with
various code rates and constraint lengths.
As a result, a simple convolutional code will be used to

describe the code properties as shown in Figure 2.

Figure 2

Encoder Representations
The encoder can be represented in several

different but equivalent ways. They are


1.
2.
3.
4.

Generator Representation
Tree Diagram Representation
State Diagram Representation
Trellis Diagram Representation

1. Generator Representation
Generator representation shows the hardware

connection of the shift register taps to the modulo-2


adders.
A generator vector represents the position of the
taps for an
output.
A 1 represents a connection and a 0 represents
no connection.
For example, the two generator vectors for the
encoder in Figure 2 are g1 = [111] and g2 = [101]
where the subscripts 1 and 2 denote the
corresponding output terminals.

2. Tree Diagram
Representation
The tree diagram representation shows all possible

information and encoded sequences for the


convolutional encoder.
Figure 3 shows the tree diagram for the encoder in
Figure 2 for four input bit intervals.

Figure 3

In the tree diagram, a solid line represents input

information bit 0 and a dashed line represents


input information bit 1.
The corresponding output encoded bits are
shown on the branches of the tree.
An input information sequence defines a specific
path through the tree diagram from left to right.
For example, the input information sequence
x={1011} produces the output encoded
sequence c={11, 10, 00, 01}. Each input
information bit corresponds to branching either
upward (for input information bit 0) or downward
(for input information bit 1) at a tree node.

3. State Diagram
Representation
The

state diagram shows the state


information of a convolutional encoder.
The state information of a convolutional
encoder is stored in the shift registers.
Figure 4 shows the state diagram of the
encoder in Figure 2.

In the state diagram, the state information of the

encoder is shown in the circles.


Each new input information bit causes a transition from
one state to another.
The path information between the states, denoted as
x/c, represents input information bit x and output
encoded bits c.
It is customary to begin convolutional encoding from the
all zero state.
For example, the input information sequence x={1011}
(begin from the all zero state) leads to the state
transition sequence s={10, 01, 10, 11} and produces
the output encoded sequence c={11, 10, 00, 01}.
Figure 5 shows the path taken through the state
diagram for the given example.

Figure 5 The state transitions (path) for input information


sequence {1011}

4. Trellis Diagram
Representation
The trellis diagram is basically a redrawing of the

state diagram.
It shows all possible state transitions at each time
step.
Frequently, a legend accompanies the trellis
diagram to show the state transitions and the
corresponding input and output bit mappings
(x/c).
This compact representation is very helpful for
decoding convolutional codes as discussed later.
Figure 6. shows the trellis diagram for the
encoder in Figure 2.

Figure 6. Trellis diagram representation of


encoder in Figure 2 for input bit intervals

Figure 7 shows the trellis path for the state


transitions in figure 5

Catastrophic Convolutional
Code
Catastrophic convolutional code causes a

large number of bit errors when only a


small number of channel bit errors is
received.
This type of code needs to be avoided and
can be identified by the state diagram.
A state diagram having a loop in which a
nonzero information sequence corresponds
to an all-zero output sequence identifies a
catastrophic convolutional code.
Figure 8 shows two examples of such code.

Figure 8 Examples of catastrophic


convolutional code

Exercise
A convolution code is described by
g1=[ 1 0 1]
g2=[ 1 1 1]
g3=[ 1 1 1]
a) Draw the encoder corresponding to this code
b) Draw the state diagram for this code
c) Draw the trellis diagram for this code
d) Verify whether or not this code is catastraphic.

Homework:
Repeat the above problem for a code with
g1=[ 1 1 0]
g2=[ 1 0 1]
g3=[ 1 1 1]

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