Sram Memory Cell: By:-Udit Shah & Rajdeep Kandiyal
Sram Memory Cell: By:-Udit Shah & Rajdeep Kandiyal
Memory Arrays
Memory Arrays
Read/Write Memory
(RAM)
(Volatile)
Static RAM
(SRAM)
Dynamic RAM
(DRAM)
Mask ROM
Programmable
ROM
(PROM)
Shift Registers
Serial In
Parallel Out
(SIPO)
Erasable
Programmable
ROM
(EPROM)
Queues
Parallel In
Serial Out
(PISO)
Electrically
Erasable
Programmable
ROM
(EEPROM)
SRAM
First In
First Out
(FIFO)
Last In
First Out
(LIFO)
Flash ROM
Slide
2
Static (SRAM)
Data stored as long as supply is applied
Large (6 transistors per cell)
Fast
Differential signal (more reliable)
Dynamic (DRAM)
Periodic refresh required
Small (1-3 transistors per cell) but slower
Single ended (unless using dummy cell to generate
differential signals)
Static SRAM(SRAM)
SRAM :Is static memory.
The term static is derived from the fact
3.Synchronous SRAM
DESIGN:-
Ax
VDD
Data line
M2
M5
M4
M6
Q
M1
M3
Ay
Write
M9
Data i/p
Data line
M8
Read
M10
M7
Data o/p
Operation
To write: W=1, M9 ON.
TYPES
A. Bipolar1.Application for ultra high speed SRAM
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